10进制加法器的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count10wm is 
port (clk,cr,s: in std_logic;
     q: out std_logic_vector(3 downto 0);
    co: out std_logic);
    bo: out std_logic);
end;
architecture behav of count10wm is 
signal po: std_logic_vector(3 downto 0);
--signal po: std_logic_vector(3 downto 0);
begin
process(clk,cr,s)
begin 
if cr='1' then po<="0000";
elsif clk'event and clk='0' then 
if s='0'  then 
if po=9 then po<="0000";
else po<=po+1;
end if;
elsif s='1' then 
if po=0 then po<="1001";
else po<=po-1;
end if;
end if;
end if;
end process;
q<=po;