9.3. Parameter...........................................................................................................84
9.4. Configuration Registers.........................................................................................84
9.5. Interface Signals..................................................................................................84
9.6. Ethernet MDIO Core Revision History......................................................................85
10. Intel FPGA 16550 Compatible UART Core....................................................................86
10.1. Core Overview...................................................................................................86
10.2. Feature Description............................................................................................ 86
10.2.1. Unsupported Features.............................................................................87
10.2.2. Interface...............................................................................................87
10.2.3. General Architecture...............................................................................89
10.2.4. 16550 UART General Programming Flow Chart........................................... 89
10.2.5. Configuration Parameters........................................................................ 91
10.2.6. DMA Support......................................................................................... 91
10.2.7. FPGA Resource Usage............................................................................. 92
10.2.8. Timing and Fmax................................................................................... 92
10.2.9. Avalon-MM Slave....................................................................................93
10.2.10. Over-run/Under-run Conditions.............................................................. 94
10.2.11. Hardware Auto Flow-Control.................................................................. 95
10.2.12. Clock and Baud Rate Selection............................................................... 96
10.3. Software Programming Model.............................................................................. 96
10.3.1. Overview.............................................................................................. 96
10.3.2. Supported Features................................................................................ 96
10.3.3. Unsupported Features.............................................................................97
10.3.4. Configuration.........................................................................................97
10.3.5. 16550 UART API.................................................................................... 97
10.3.6. Driver Examples...................................................................................101
10.4. Address Map and Register Descriptions ...............................................................105
10.4.1. rbr_thr_dll...........................................................................................106
10.4.2. ier_dlh................................................................................................ 107
10.4.3. iir.......................................................................................................109
10.4.4. fcr......................................................................................................110
10.4.5. lcr...................................................................................................... 112
10.4.6. mcr.................................................................................................... 113
10.4.7. lsr...................................................................................................... 114
10.4.8. msr.................................................................................................... 116
10.4.9. scr..................................................................................................... 118
10.4.10. afr.................................................................................................... 119
10.4.11. tx_low...............................................................................................120
10.5. Intel FPGA 16550 Compatible UART Core Revision History......................................120
11. UART Core.................................................................................................................122
11.1. Core Overview................................................................................................. 122
11.2. Functional Description.......................................................................................122
11.2.1. Avalon-MM Slave Interface and Registers.................................................122
11.2.2. RS-232 Interface..................................................................................123
11.2.3. Transmitter Logic..................................................................................123
11.2.4. Receiver Logic......................................................................................123
11.2.5. Baud Rate Generation........................................................................... 124
11.3. Instantiating the Core....................................................................................... 124
11.3.1. Configuration Settings...........................................................................124
Contents
Embedded Peripherals IP User Guide
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