I2C.zip_LPC1114_SysTick_Delay.h_lpc1114 i2c

/**************************************************************************//** * @file system_LPC11xx.c * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File * for the NXP LPC11xx/LPC11Cxx Devices * @version V1.10 * @date 24. November 2010 * * @note * Copyright (C) 2009-2010 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #include <stdint.h> #include "LPC11xx.h" /* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ /*--------------------- Clock Configuration ---------------------------------- // // <e> Clock Configuration // <h> System Oscillator Control Register (SYSOSCCTRL) // <o1.0> BYPASS: System Oscillator Bypass Enable // <i> If enabled then PLL input (sys_osc_clk) is fed // <i> directly from XTALIN and XTALOUT pins. // <o1.9> FREQRANGE: System Oscillator Frequency Range // <i> Determines frequency range for Low-power oscillator. // <0=> 1 - 20 MHz // <1=> 15 - 25 MHz // </h> // // <h> Watchdog Oscillator Control Register (WDTOSCCTRL) // <o2.0..4> DIVSEL: Select Divider for Fclkana // <i> wdt_osc_clk = Fclkana/ (2 � (1 + DIVSEL)) // <0-31> // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) // <0=> Undefined // <1=> 0.5 MHz // <2=> 0.8 MHz // <3=> 1.1 MHz // <4=> 1.4 MHz // <5=> 1.6 MHz // <6=> 1.8 MHz // <7=> 2.0 MHz // <8=> 2.2 MHz // <9=> 2.4 MHz // <10=> 2.6 MHz // <11=> 2.7 MHz // <12=> 2.9 MHz // <13=> 3.1 MHz // <14=> 3.2 MHz // <15=> 3.4 MHz // </h> // // <h> System PLL Control Register (SYSPLLCTRL) // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) // <i> F_clkin must be in the range of 10 MHz to 25 MHz // <i> F_CCO must be in the range of 156 MHz to 320 MHz // <o3.0..4> MSEL: Feedback Divider Selection // <i> M = MSEL + 1 // <0-31> // <o3.5..6> PSEL: Post Divider Selection // <0=> P = 1 // <1=> P = 2 // <2=> P = 4 // <3=> P = 8 // </h> // // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL) // <o4.0..1> SEL: System PLL Clock Source // <0=> IRC Oscillator // <1=> System Oscillator // <2=> Reserved // <3=> Reserved // </h> // // <h> Main Clock Source Select Register (MAINCLKSEL) // <o5.0..1> SEL: Clock Source for Main Clock // <0=> IRC Oscillator // <1=> Input Clock to System PLL // <2=> WDT Oscillator // <3=> System PLL Clock Out // </h> // // <h> System AHB Clock Divider Register (SYSAHBCLKDIV) // <o6.0..7> DIV: System AHB Clock Divider // <i> Divides main clock to provide system clock to core, memories, and peripherals. // <i> 0 = is disabled // <0-255> // </h> // </e> */ #define CLOCK_SETUP 1 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 /* //-------- <<< end of configuration section >>> ------------------------------ */ /*---------------------------------------------------------------------------- Check the register settings *----------------------------------------------------------------------------*/ #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) #define CHECK_RSVD(val, mask) (val & mask) /* Clock Configuration -------------------------------------------------------*/ #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) #error "SYSOSCCTRL: Invalid values of reserved bits!" #endif #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) #error "WDTOSCCTRL: Invalid values of reserved bits!" #endif #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) #error "SYSPLLCLKSEL: Value out of range!" #endif #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) #error "SYSPLLCTRL: Invalid values of reserved bits!" #endif #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) #error "MAINCLKSEL: Invalid values of reserved bits!" #endif #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) #error "SYSAHBCLKDIV: Value out of range!" #endif /*---------------------------------------------------------------------------- DEFINES *----------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define __XTAL (12000000UL) /* Oscillator frequency */ #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) #if (CLOCK_SETUP) /* Clock Setup */ #if (__FREQSEL == 0) #define __WDT_OSC_CLK ( 0) /* undefined */ #elif (__FREQSEL == 1) #define __WDT_OSC_CLK ( 500000 / __DIVSEL) #elif (__FREQSEL == 2) #define __WDT_OSC_CLK ( 800000 / __DIVSEL) #elif (__FREQSEL == 3) #define __WDT_OSC_CLK (1100000 / __DIVSEL) #elif (__FREQSEL == 4) #define __WDT_OSC_CLK (1400000 / __DIVSEL) #elif (__FREQSEL == 5) #define __WDT_OSC_CLK (1600000 / __DIVSEL) #elif (__FREQSEL == 6) #define __WDT_OSC_CLK (1800000 / __DIVSEL) #elif (__FREQSEL == 7) #define __WDT_OSC_CLK (2000000 / __DIVSEL) #elif (__FREQSEL == 8) #define __WDT_OSC_CLK (2200000 / __DIVSEL) #elif (__FREQSEL == 9) #define __WDT_OSC_CLK (2400000 / __DIVSEL) #elif (__FREQSEL == 10) #define __WDT_OSC_CLK (2600000 / __DIVSEL) #elif (__FREQSEL == 11) #define __WDT_OSC_CLK (2700000 / __DIVSEL) #elif (__FREQSEL == 12) #define __WDT_OSC_CLK (2900000 / __DIVSEL) #elif (__FREQSEL == 13) #define __WDT_OSC_CLK (3100000 / __DIVSEL) #elif (__FREQSEL == 14) #define __WDT_OSC_CLK (3200000 / __DIVSEL) #else #define __WDT_OSC_CLK (3400000 / __DIVSEL) #endif /* sys_pllclkin calculation