Table of Contents
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution..........4
Introduction................................................................................................................................. 4
Features........................................................................................................................................4
Using MIG in the Vivado Design Suite...................................................................................... 5
Synplify Pro Black Box Testing.................................................................................................71
Core Architecture...................................................................................................................... 73
Designing with the Core.........................................................................................................144
Interfacing to the Core........................................................................................................... 144
Customizing the Core............................................................................................................. 160
Design Guidelines................................................................................................................... 170
Debugging DDR3/DDR2 Designs.......................................................................................... 203
Chapter 2: QDR II+ Memory Interface Solution.........................................247
Introduction............................................................................................................................. 247
Using MIG in the Vivado Design Suite.................................................................................. 248
Core Architecture.................................................................................................................... 289
Customizing the Core............................................................................................................. 306
Design Guidelines................................................................................................................... 311
Debugging QDR II+ SRAM Designs.......................................................................................319
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface
Solutions......................................................................................................................349
Introduction............................................................................................................................. 349
Using MIG in the Vivado Design Suite.................................................................................. 350
Core Architecture.................................................................................................................... 397
Customizing the Core............................................................................................................. 430
Design Guidelines................................................................................................................... 437
Debugging RLDRAM II and RLDRAM 3 Designs.................................................................. 452
Chapter 4: LPDDR2 SDRAM Memory Interface Solution....................... 486
Introduction............................................................................................................................. 486
Features....................................................................................................................................486
UG586 (v4.2) May 30, 2024
Zynq 7000 SoC and 7 Series FPGAs MIS v4.2 2
