DDR Simulation Tutorial - DIMMonBoard
Product Version Sigrity 2018
March 2019
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Contents
1
Introduction
Overview
Sample Case
Pre-Setup Sample Files
Post_Setup Sample Files
Result Files
2
Layout Setup
Load Layout File
Check Stackup
3
Bus Group Generation and Models Assignment
Generate Bus Group
Select Memory Controller
Select Memory Components
Assign Signal Net to Power/Ground Nets
Select VRM Component and Assign Voltage Level
Assign Bus Group and Net Properties
Preview Bus Groups
Assign Capacitor Models
Setup Controller IBIS Model
Assign IO Buffer Models to Signal Pins
Define Power/Ground Net Models and Pin Mapping
4
Memory Models Setup
Setup Memory Models for J1
Load DIMM Connector Subcircuit Model
Generate MCP Pins for DIMM Connector ckt Model
Connect DIMM Connector Model MCP Pins to Layout DIMM Component
Load DIMM S-parameter Model
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Table of Contents
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Generate XNet for DIMM S-parameter Model
Connect DIMM S-parameter Model to DIMM Connector Model
Assign IBIS Model to DRAM
Setup Memory Model for J2
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Write: Setup DDR Analysis Options
Select Bus Groups and Signal Nets for simulation
Setup Analysis Options
Run Simulation and View Result
Save file and start simulation
View Result
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Read: Setup DDR Analysis Options
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Generate DDR Simulation Report
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DDR Simulation Tutorial - DIMMonBoard
Table of Contents
1
Introduction
Overview
This tutorial introduces how to set up layout based DDR simulation with DIMM on board using
SPEED2000. The main board contains one controller, two DIMMs, one VRM and some decaps.
The simulation setup is in main board layout environment. The main steps include:
1. Generate bus groups and set up VRM component and voltage.
2. Add controller IBIS model at controller component footprint.
3. Connect models at each DIMM component footprint:
Attach DIMM connector model
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DDR Simulation Tutorial - DIMMonBoard
Introduction
