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Introduction to Computing Systems from Bits and Gates to C and Beyond.pdf 2nd Edition [English] 本书是计算机系统概论的英文原版,计算机科学的经典基础教材。全书以自底向上方法帮助学生理解计算机系统的原理,前半部分阐述了计算机底层结构,后半部分讲解了高级语言编程及编程方法学,主要内容包括数据类型及其运算、数字逻辑、冯·诺伊曼模型、汇编语言、输入和输出、TRAP程序和子程序、C语言编程等内容。 本书可用作高等院校计算机及相关专业学生的入门教材,也可作为的计算机专业人土和高级程序员的参考用书。 作者:(美)派特(Patt.Y.N.),(美)派特尔(Patel,S.J.)
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introduction to
computing systems

The
McGraw-Hill Companies
Mc
Graw
Hill
INTRODUCTION TO COMPUTING SYSTEMS: FROM BITS AND GATES TO C AND BEYOND
SECOND EDITION
International Edition 2005
Exclusive rights by McGraw-Hill Education (Asia), for manufacture and export. This book cannot be
re-exported from the country to which it is sold by McGraw-Hill. The International Edition is not
available in North America.
Published by McGraw-Hill, a business unit of The McGraw-Hill Companies, Inc., 1221 Avenue of the
Americas, New York, NY 10020. Copyright © 2004, 2001 by The McGraw-Hill Companies, Inc. All
rights reserved. No part of this publication may be reproduced or distributed in any form or by any
means, or stored in a database or retrieval system, without the prior written consent of The McGraw-
Hill Companies, Inc., including, but not limited to, in any network or other electronic storage or
transmission, or broadcast for distance learning.
Some ancillaries, including electronic and print components, may not be available to customers outside
the United States.
10 09 08 07 06 05 04 03 02 01
20 09 08 07 06 05 04
CTF SEP
Cover images: ©Photodisc, AA048376 Green Abstract, AA003317 Circuit Board Detail
Library of Congress Control Number: 2003051002
When ordering this title, use ISBN 007-124501-4
Printed in Singapore

> > second edition
introduction to
computing systems
from bits and gates to C and beyond
Yale N. Patt
The University of Texas at Austin
Sanjay J. Patel
University of Illinois at Urbana-Champaign
Mc
Graw
Hill
Higher Education
Boston Burr Ridge, IL Dubuque, IA Madison, Wl New York San Francisco St. Louis
Bangkok Bogota Caracas Kuala Lumpur Lisbon London Madrid Mexico City
Milan Montreal New Delhi Santiago Seoul Singapore Sydney Taipei Toronto

To the memory of my parents,
Abraham Walter Patt A"H and Sarah Clara Patt A"H,
who taught me to value "learning"
even before they taught me to ride a bicycle.
To Mira and her grandparents,
Sharda Patel and Jeram Patel.

contents
Preface xi
Preface to the First Edition
1 Welcome Aboard 1
XVII
2.4.1 Binary to Decimal Conversion 27
2.4.2 Decimal to Binary Conversion 28
1.1
1.2
1.3
1.4
1.5
1.6
1.7
What We Will Try to Do 1
How We Will Get There 2
Two Recurring Themes 3
1.3.1 The Notion of Abstraction 3
1.3.2 Hardware versus Software 5
A Computer System 7
Two Very Important Ideas 9
Computers as Universal Computational
Devices 9
How Do We Get the Electrons to Do the
Work?
1.7.1
1.7.2
1.7.3
1.7.4
1.7.5
1.7.6
1.7.7
1.7.8
Exercises 17
12
The Statement of the Problem 13
The Algorithm 13
The Program 14
The ISA 14
The Microarchitecture 15
The Logic Circuit 16
The Devices 16
Putting It Together 16
2 Bits, Data Types, and
Operations 21
2.1
2.2
2.3
2.4
Bits and Data Types 21
2.1.1 The Bit as the Unit of
Information 21
2.1.2 Data Types 22
Integer Data Types 23
2.2.1 Unsigned Integers 23
2.2.2 Signed Integers 23
2's Complement Integers 25
Binary-Decimal ..Conversion 27
2.5 Operations on Bits—Part I: Arithmetic
2.5.1 Addition and Subtraction 29
2.5.2 Sign-Extension 30
2.5.3 Overflow 31
2.6 Operations on Bits—Part II: Logical
Operations 33
2.6.1
v
The AND Function 33
2.6.2 The OR Function 34
2.6.3 The NOT Function 35
2.6.4 The Exclusive-OR Function 35
2.7 Other Representations 36
2.7.1 The Bit Vector 36
2.7.2 Floating Point Data Type 37
2.7.3 ASCII Codes 40
2.7.4 Hexadecimal Notation 41
Exercises 43
3 Digital Logic Structures 51
3.1 The Transistor 51
3.2 Logic Gates 53
3.2.1 The NOT Gate (Inverter) 53
3.2.2 OR and NOR Gates 54
3.2.3 AND and NAND Gates 56
3.2.4 DeMorgan's Law 58
3.2.5 Larger Gates 58
3.3 Combinational Logic Circuits 59
3.3.1 Decoder 59
3.3.2 Mux 60
3.3.3 Full Adder 61
3.3.4 The Programmable Logic Array
(PLA) 63
3.3.5 Logical Completeness 64
Basic Storage Elements 64
3.4.1 The R-S Latch 64
3.4.2 The Gated D Latch 66
3.4.3 A Register 66
29
3.4
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