Palnitkar_verilog HDL数字设计与综合(第二版）_课后习题答案

Chap 7 ------ File Name Description Reference in Book --------- ----------- ----------------- initial.v Illustrates the use of Section 7.1.1 the initial statement. always.v Illustrates the use of Section 7.1.2 the always statement. block.v Illustrates the blocking Section 7.2.1 procedural assignment. nonblock.v Illustrates the non- Section 7.2.2 blocking procedural assignment. reg_del.v Illustrates regular Section 7.3.1 delay control. event_or.v Illustrates control using Section 7.3.2 the event based timing control. demux1_4.v Example of a 1-to-4 Section 7.5.1 demultiplexer using the the case statements. while1.v Illustrates the use of Section 7.6.1 while loop to count from Illustration 1 0 to 127. while2.v Illustrates the use of Section 7.6.1 while loop to find the Illustration 2 true bit in a number. for.v Illustrates the use of Section 7.6.2 for loop to count from 0 to 127. repeat1.v Illustrates the use of Section 7.6.3 repeat loop to count from Illustration 1 0 to 127. repeat2.v Illustrates the use of Section 7.6.3 repeat loop to count Illustration 2 a certain number of cycles. forever1.v Illustrates the use of Section 7.6.4 forever loop to generate Illustration 1 clock forever2.v Illustrates the use of Section 7.6.4 forever loop to Illustration 2 synchronize registers. seq.v Illustrates the sequential Section 7.7.1, Seq Block block with begin-end Illustration 2 parallel.v Illustrates the parallel Section 7.7.1, Parallel Block block with fork-join Illustration 1 nested.v Illustrates nested blocks. Section 7.7.2 disable.v Explains how to disable Section 7.7.2 named blocks. mux4_1.v Illustrates a 4-to-1 Section 7.9.1 multiplexer using behavioral case statement. counter.v Illustrates a 4-bit binary Section 7.9.2 counter. sig_ctrl.v Illustrates the design Section 7.9.3 of a traffic signal controller.