Cher3 2 (Ver 1.7) en
Cher3 2 (Ver 1.7) en
(version 1.7)
Inventory
Chapter 1. NB scheme Chapter 2. POWER Chapter 3. CHARGE Chapter 4. CLOCK Chapter 5. HDMI Chapter 6. Touch Pad Chapter 7. Keyboard Chapter 8. AUDIO P5~P77 P78~P185 P186~P223 P224~P247 P248~P261 P262~P279 P280~P292 P293~P328
Inventory
Chapter 9. MODEM Chapter 10. USB Chapter 11. PCMCIA Chapter 12. IEEE 1394 Chapter 13. Card Reader Chapter 14. SATA Chapter 15. ODD Chapter 16. LAN P329~P338 P339~P358 P359~P363 P364~P380 P381~P393 P394~P400 P401~P409 P410~P430
Inventory
Chapter 17. VGA Chapter 18. LCD Chapter 19. BIOS Chapter 20. MEMORY Chapter 21. POST CODE Chapter 22. NEW CARD Chapter 23. EC P431~P446 P447~P485 P485~P511 P512~P538 P539~P584 P585~P590 P591~P621
Chapter 1 NB scheme
Overview
Introduction Diagram Q & A (Repair Experience)
Introduce
Intel Product AMD Product EeePC Product
Support DDR
CPU Catch (L2) GMCH (FSB) ICH Wi-Fi
(802.11)
Huron River
Sandy Bridge (32nm)
DDR3-1066/1333
CPU Code
Support DDR CPU Catch (L3) ICH Wi-Fi
4/8 (8 M) QS67, QM67, HM67, HM65, UM67 Centrino Advanced-N + WiMAX 6150
Montevina vs Calpella
Diagram
Sonoma Platform Napa Platform Santa Rosa Platform Montevina Platform Calpella Platform Sandy Bridge Platform
CPU
Dothan
CRT
400/533 MHz FSB DDR2 SDRAM 400/533 MHz DDR1 SDRAM 333 MHz Dual Channel support DDR2 Single Channel support DDR1
Alviso
(GMCH) 915GM
Memory DIMM
1 x SODIMM socket for expansion up to 768GB DDR2-400/533 DRAM support PCI BUS ,33MHz
USB 2.0
IDE BUS Ultra ATA 100/66ICH6-M 2.5 30/40/60/80 GB 4200/5400RPM Azalia Link
Cardbus R5C841
RJ-45
IEEE 1394
PCMCIA type II
Modem Module
KBC M38857
CPU
Yonah
Intel Yonah dual core T2300/2400/2500/2600 1.66/ 1.83/ 2.0/ 2.16G Processor 2MB On-Die L2 Cache
667 MHz FSB DDR2 SDRAM 533/667 MHz Single or Dual Channel support
Calistoga
(GMCH) 945GM
Memory DIMM
Bluetooth V2.0
DMI Link ,100MHz (Direct Media Interface) PCI BUS 3.3V ,33MHz Azalia Link
Cardbus R5C832
RJ-45
KBC M38857
Modem Module
5 IN 1 Card Reader
AMD Platform
Among Danube platform system, chip group adopt three chip structural design, monobasic M880G (RS880M) at north bridge chip continue to use still ,But the chip of south bridge is upgraded from SB710 to SB820 M, the north bridge combines Mobility Radeon HD 4200 figure core, obility Radeon HD 5000 series to do for the independent display card and its matching. Besides supporting DDR3 SO-DIMM memory, AMD Danube platform also supports SATA 6Gbps high-speed interface, DVI/HDMI/DisplayPort video to expand interfaces, and the generator of the integrated clock and a new generation's wireless technology.
Eeepc Platform
Diamondville
PineTrail
Diamondville
PineTrail
Atom N270 Atom N280 Atom N450 Atom D410 Atom D450 FSB 1.66GHZ 1/2 533MHZ 1.66GHZ 1/2 667MHZ 1.66GHZ 1/2 667MHZ 1.66GHZ 1/2 800MHZ 1.66GHZ 2/4 800MHZ
L2
TDP
512KB
45nm 2.5W
512KB
45nm 2.5W
512KB
45nm 5.5W
512KB
45nm 10W
2*512KB
45nm 13W
2 3
1 2
Socket A Athlon XP
Overview
Introduction Diagram Repair Flow Chart Q & A (Repair Experience)
Introduction
Classification of the power circuit Linear & Switching Regulator Switching Buck Converter Voltage & Current Mode Control Multiple Output Controller Multi-Phase Operation
DCAC: Inverter.
ACAC: AC Converter.
Linear Regulator
INPUT REF - + OUTPUT
Linear Regulator
Advantages
Simple Low Cost
Issues
Power Dissipation
Switching Regulator
Switching Regulator
Advantages
Efficient
Issues
Noise Layout
PWM controller
FB GND
UGATE PHASE
VOUT
PWM controller
FB
VOUT
GND
CONTROL IC
VOUT
VIN
PWM LOGIC
VOUT
VOLTAGE CONTROL
Diagram
Santa Rosa Power Plane Standard Diagram
(A8S,A8E,F3E,F7Sr,F9S,W7S,Z96S..etc.)
Diagram-1
(Santa Rosa )
Diagram-2-1
(Montevina)
Diagram-2-2
(Montevina)
Diagram-3
(Calpella)
Diagram-4
(Sandy Bridge)
Diagram-5
(AMD Puma)
Diagram-6
(Diamondville Puma)
Diagram-7
(PineTrail Puma)
Confirm the circuit, Check All Always/ Stand-by Voltage (ex. +3V/+5V always) (by RD design)
Change NG Component
Trace and confirm the circuit to Check 1.PWR_SW# status Hi->Lo->Hi and Lid_SW# signal must be always Hi 2.PWR_BTN# signal status Lo->Hi->Lo (to S.B) (all status Hi or Lo will be by RD Design spec.) 1.PM_SUSC# +3V , +5V +12V etc (by model request) 2.PM_SUSB# +12Vs , +3Vs , +5Vs..etc (by model request) 3.CPUVR_ON Vcore , VRM_PWRGD , CLK_EN#
Finished
Confirm the TSICT program, Check what kind voltage of ICT Power jump (+3V or +3Vs / +5V or +5Vs .)
Confirm & check to separate which power circuit cause AC_BAT_SYS to GND
()Separate
ICT power Jump solder, Use multi-Meter to measure which side voltage to GND ()Confirm the circuit and use TSICT program to Find out all the connection component Check Item as follow: (1)Check MOS-FET component (G-S gate is no short) (2)Check Capacitor (V.I capacitor surface is no rift) (3)Change voltage to GND of BGA component Finish
Power circuit can differentiate to 4 section : ()Main Power IC circuit Check MOS-FET ,Capacitor ,Power IC ()BATT charge circuit Check MOS-FET ,Capacitor ,Diode ,Charge IC ()CPU Vcore Power circuit Check MOS-FET ,Capacitor ,Diode ,CPU power IC ()LCD Inverter Power supply circuit Check Capacitor or Inductance
NB power training
--For Montevina platform
Keyboard matrix/Touchpad control Power/ChargerLEDs instruct Fan tachometer control Power management (sleep/hibernate/wake up/Lid switch) Power sequence control with ICH9M Battery charger/cell capacity/temperature monitor GPIO control
PS: If the system cannt power on, we can snatch LPC_FRAME# to make known that whether EC has worked.
ACPI (Advanced Configuration and Power Interface, advanced configuration and power interface) It is by Intel, Unless Microsoft, Phoenix, HP and computer powers that Toshiba make together last specification, it last operating system can Utilize the state of power with various devices of direct management.
G0/S0:Full on G1/S1:CPU sleep ----SB(EXP:ICH9M) has the option to assert the CPUSLP# signal to further reduce processor power consumption. G1/S3:Suspend to RAM ----The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except RTC clock. G1/S4:Suspend to Disk ----The context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.
G2/S5:Soft off ----System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.
G3:Mechanical off ----power failure Because the system does not have any power.
1
VSUS_ON -> 0 PM_RSMRST# -> 0
end
end
Wait VSUS_GD=1
1
PM_PWRBTN# -> 1 Delay 20ms PM_RSMRST# -> 1
end
sequence
2.A/D_DOCK_I N
CPU
20.H_CPU_RST#
MAX8725
3.AC_BAT_SYS
4.+3V A
16.VRM_PWRGD
8.PM_RSMRST#
9.PWR_SW # 4.AC_OK=1
10.PWRBTN#
11.PM_SUSC#
12.PM_SUSB#
RTC BAT
SB ICH9M
17.PM_PWROK
5.VSUS_O N
RT8203
1.RTCRST#
EC ITE8752
Vcore controller
16.VRM_PWRGD
sequence
2.BAT_CON
CPU
20.H_CPU_RST#
MAX8725
3.AC_BAT_SYS
4.+3V A
16.VRM_PWRGD
9.PM_RSMRST#
5.PWR_SW # 4.AC_OK=0
10.PWRBTN#
11.PM_SUSC#
12.PM_SUSB#
RTC BAT
SB ICH9M
17.PM_PWROK
6.VSUS_O N
RT8203
1.RTCRST#
EC ITE8752
Vcore controller
16.VRM_PWRGD
Common Bugs(1)
1.The system cannt be powered on, and the adaptor LED indication flicker.
Here is somewhere short, check all power rails whether have been short to GND.
2.The system cannt be powered on, and power LED not lighten.
Maybe The BIOS ROM content has been wrecked. +3VA powered? Why not VSUS power? Power IC or MOSFET or Diode burnout?
3.The power LED lighten, but the system cannt bring up to DOS.
plug in debug card, view the 80 post code, for example:
80 code no motion, show 00 > CPU not work >measure power sequence black screen, show d0~d5 > memory plug failed or memory broken black screen, show F0~F2 > one DIMM slot failed show 38 > check USB port and USB device
If not mount LPC debug & Newcard debug card because of cost down, try to flash BIOS by JIG board or measure sequence.
Common Bugs(2)
5.take a software bug on M51A for example in Vista, can use hotkeys Fn+F5 & Fn+F6 to control backlight brightness, but in XP, these hotkeys have no function
Vista: report to driver directly to active but XP: need report to BIOS, and it send software SCI to active. solution: update BIOS to 217 or newer version
NB power training
--For calpella platform
Outline
Charger MB39A132
1.Adapter/battery exchange 2.Chang to prepare 3.MB39A132 chargings Establishment 4.MAX8725 chargings Establishment 5.MAX17015 chargings Establishment
Vcore RT8856
1.Montevina platform VS Calpella (power) 2.VIDs Establishment setp 3.Powet sequence
System RT8206/RT8202
1.RT8206 2.RT8202
Power-flow
Vcore RT8856
1 Montevina platform VS Calpella (power)
Item
chipsets Power rail power Memory Support VID/ Vboot DAC codes Vboot Monitor Power saving signal DPRSLPVR
Montevina (IMVP6+)
3(CPU+NB+SB) Vcore(core) DDR2(1.8V) VID[6:0] 1.2V PMON 3.3V-H
Calpella (IMVP6.5)
2(CPU+Ibex Peak-M) VGFX (Graphics)/ Vcore (core) /VTT-CPU(core) DDR3(1.5V) VID[6:0] 1.1V IMON Vttcpu-H
DPRSTP#
Performance other Performance OVP
Support slow C4
/X 1.7V
deleted
Turbo boost 1.55V
2VIDs Establishment
POC (power on configuration) line: Vcore power pull high beforeCPU will pass VID[5:3] step to know VR Imax;
VID[2:0],VID[6],DPRSLPVR,PSI #---default; CPU will passVR .IMON will know Vcore and GFX-corespower; Turbo Boost Technology: CPU Core and GFX Core make power sharing improve thrt performance
3Power sequence
Wait system power OK afterEC will pull CPU_VRON to HighVcore power than to upVRM_PWRGD pull high after 6ms..
GFX core no need to Establishment POC lineVID pull H/L only for factory ATS test(No put in CPU,VID floating)DPRSLPVR no need to Establishment default; CPU pass VRIMON to know GFX-corespower; Turbo Boost Technology
2Power sequence
GFX Core power between VTT_CPU power after Vcore power befer CPU Send GFX_VRON news power level is CTT_CPU
system RT8206/RT8202
1RT8206
RT8206s work principle the same RT8205 +3VA open by +5VA than pass LDO to output.
Q&A
Q1:MAX8725, MAX17015 charge the principle. Leave ADAPTER show battery icon, leave the battery show ADAPTER icon, except consider AC _ IN _ OC# and BAT _ IN _OC# What signals does need considering? A: first need check adapter and battery are OK or not =>And then see AC _ IN _ OC # and BAT _ IN _ OC#(TS1#) Connect it by mistake =>Confirm whether EC is OK
Q2Q2: RT8206 operation principleK40C use this chipa lot of 3vo and 5vo are loss,so dont boot AWant this pieces of question according to at check forward step by step: Confirm first whether the board or component are damaged =>After having the power, AC_BAT_ SYSwhether the voltage =>Is 5VA OK =>Is 3VA OK =>VSUS_ON stand up =>If no 3VO/5VO voltage, should be change controller .
AC_BAT_SYS Y
+3VA Y
SUS
Y SUSC Y SUSB Y CPU
Y
VSUS_ON
N Y
SUSC_EC#
EC Damage
IC/MOS Damage
Y
SUSC_EC# IC/MOS Damage
Y
CPU_VRON IC/MOS Damage
EX1:
Adapter indicator lamp to glimmers ceaselessly
AC indicator lamp to glimmers ceaselessly AC_BAT_SYS N
Device short to GND
Battery
NB,SB to GND
EX2
NO +3VSUS,+5VSUS voltage AC
N +3VA Y
N +3VA Y
EC Damage
RT8206 Damage
VSUS_ON
Y
measure MOS OK?
N
Change MOS
Y
IC Damage
.Link JP of below
AC in
EC short to GND
EX3
NB dont charge
Battery is it intact
EC Damage
Change MOS
EX4
No VCORE voltage
Other power Ok?
N
CPU_VRON
EC Damage
Y
Measure MOS OK?
N
MOS
Y
IC Damage
NB power training
--For Sandy Bridge platform
NB power training
--For AMD platform
S5S0
S3S0
Problems
1.The system cannt be powered on, and the adaptor LED indication flicker.
Here is somewhere short, check all power rails whether have been short to GND.
2.The system cannt be powered on, and power LED not lighten.
Maybe The BIOS ROM content has been wrecked. +3VA powered? Why not VSUS power? Power IC or MOSFET or Diode burnout?
3.The power LED lighten, but the system cannt bring up to DOS.
plug in debug card, view the 80 post code, for example:
80 code no motion, show 00 > CPU not work >measure power sequence black screen, show d0~d5 > memory plug failed or memory broken black screen, show F0~F2 > one DIMM slot failed
If not mount LPC debug because of cost down, try to Newcard port, flash BIOS by JIG board or measure sequence.
Problems
When normal voltage and frequency are still not open where do you begin. Disconnect all Device, re-plug DIMM, flash EEPROM,, confirm all reset nets, check Debug code Blue screen, crashes, cant into the system, where do you begin Disconnect all Device, re-plug DIMM, flash EEPROM, replace the HDD, check the FAN & Thermal module, search Windows error code Keyboard string key, for the EC and keyboard interface, keyboard interface to ground resistance is normal, what issues need to be considered. Replace the keyboard, re-weld, check the EMI capacitor
Problems
Start soon shot down for no reason Check thermal pip & fan is not connected correctly.
Problems
Boot no display, but the debug card can run code Check LVDS cable is not connected Check LVDS cable is bad
NB power training
--For EeePC(1008HA) platform
G3
BAT ADP S5/S4 BAT ADP S3 BAT ADP
S0
BAT
Power on sequence
Sym
Timing Parameters
Min
Max
Unit
Ta
10
us
Tb
100
us
Tc
10
us
Td
10
ms
Te
0.05
20
ms
Tf
10
BCLKs
Tg
ms
Outline
Block Diagram Features Power on sequence Common bug analyze on 1008HA Q&A Appendix
Debug flow
No ADP in ADP LED flickering yes There is somewhere short Check VA SUS power Check Charger circuit AD_DOCK_IN, AC_BAT_SYS Check +3VA Of f Open the short pin between +3VA & +3VAO On EC/SPI ROM Damage On Press power bottom Power LED on Of f Check VSUS_ON On Of On f Check RT8205D circuit
Refresh Bios Check Drivers & AP Or is there any virus? Not solve Solve Use OEM Image No OK Check Bios menu SATA IDE/AHCI mode (default AHCI) Check HDD System stable Check PM_RSMRST# , PM_PWRBTN#, SUSB# & SUSC# Ok Low
OK
EC EOS Issue
Symptom:
1. PWR LED doesnt light while pressing power bottom 2. VSUS power arent ready (VSUS_ON isnt High) 3. Refresh Bios doesnt work 4. There is some evident damage on EC chip
Root cause:
1. FFC cable plug/unplug when the system is not in G3 states (Mechanical OFF) 2. FFC cable doesn't plug well and the system is not in G3 states (AC or Battery plug in)
Outline
Block Diagram Features Power on sequence Common bug analyze on 1008HA Appendix
Outline
Block Diagram Features Power on sequence Common bug analyze on 1008HA Q&A Appendix
NB power training
--For EeePC(1201HA) platform
Agenda
Power Solution Introduction Common Bug Criteria and Solution
Power Solution
Power flow
Power Schematic
Always Power
Power Rail Control
EX:3VA,5VA /X (*)
Standby Power
EX:3VSUS,5VSUS VSUS_ON
Dual Power
EX:1.8V SUSC_ON
Main Power
EX:3VS,5VS SUSB_ON EX:VCCP CPU_VRON
(*):Because of the power latch circuit, theres no always power when only insert battery.
2.Power flow
EMB24B03G (SWITCH) AC_APR_UC_10 A/D_DOCK_IN MB39A132 (Controllor) BAT CHG_ACOK#_10 RT8205CGQW (Controller) 3VSUS: Hi-side: EMB20N03V Low-side: EMB20N03V 5VSUS: Hi-side:EMB20N03V Low-side:RJK0355 VSUS_ON SUSC_ON SUSB_ON VSUS_ON +3VSUS (4A) SUSC_ON SUSC_ON RT8202APQW (Controller)
1.8V: Hi-side:EMB20N03V Low-side: EMB20N03V
CHARGER
AC_BAT_SYS
(under0.45A) +5VA
UP7714 (LDO)
+3VA
(0.1A)
+3VS +3V
UP7714 (LDO)
(1.5A)
+1.8V (3A)
VTT_DDR (0.5A)
+1.5VS (1A)
+VCCP (5.5A)
EMB20N03V (MOS)
+VCCP_C6 (2A)
SYSTEM
+VCORE
(4A)
VRM_PWRGD
3.Power Schematic
Load Switch
Linear circuit
Switching circuit
Charger circuit
Power Latch circuit
a) Load switch
PQ28 EMB20N03V 8 7 6 S 5 5D G PR116 P_3VS5VS_EN_10
1 1 00 KOhm 3 PRN5 9B 1 00 KOhm PRN5 9A
+5VA
+12VSUS
1 1
PT 23 PT 27
1 62KOhm 1%
1
+3VS,+5VS EN
PRN59C 6 5 100KOhm
1 PT 28 1
GND
3 P_SUSB# _ON_ 10 2 4
PT 24
PQ30A 2 PQ30B
1
UM6K1N
+5VSUS
Shape
PQ29 EMB20N03V 8 7 6 S 5 5D G
1 2 3 4
(1.5A)
+5VS +5V_USB
PC112 1UF/16V
2
70Ohm /100Mhz
5
4
PC113 0.01UF/16V /X
GND
GND
S0 S5 S3/S5
GND
GND
b) Linear circuit
VTT_DDR / 0.5A
+1.8V
+5V S P L1 4 7 0Ohm /1 00 Mhz 2 5mil 1 2 3 4 P U7A V IN GND1 RE FIN V OUT GND2 NC3 NC2 V CNT L NC1 9 8 7 6 5
+1.8V
1 1
P T 36 P T 35
1 5mil GND
+VT T _ DDR
P C83 1 0UF/6 .3 V
P C84 1 0UF/6 .3 V
GND
GND
GND
1
P R14 0 1 0K Ohm
GND
GND GND
+2.5VS / 150mA
E N NC/SS /FB GND V IN V OUT P U9 UP 77 14 B MA5 -00 5 4 P R10 9 1 0K Ohm 1% P R10 8 P JP 2 0 2 2K Ohm 1 % P _2 .5V S _FB _11 0 2 _2 .5V S _FB JP2 10 P _ 1
GND
P R10 7 0 Oh m
P _2 .5V S _S HDN#_ 10 1 2 3
1 UF/16 V
P C10 1
P C10 2 1 UF/16 V /X
1 1 0UF/6 .3 V 1
P T 32 P T 31
GND
+3VA_AEC / 100mA
+5V A P T 22 T P C26 T /X +5V A
P C25 2
2 20 PF/50 V /X 1
P T 11 T P C26 T /X
P _3 V A -E C_ E N_ 10 1 2 3
+3V A
P C27 1 UF/16 V
P C28 0 .1 UF/16 V
P R34 1 0K Ohm
c 06 03
GND
GND GND
+1.8V
+1.5VS / 1A
P T 40 1 +5V S P U12 A P R11 0 1 0K Ohm 2 1 P _1 .5V S _E N_ 10 P _1 .5V S _V IN_S 1 2 3 4 P OK EN V IN CNT L GND2 GND1 FB V OUT NC GND 9 P R11 1 8 6 .3 4K Oh m 7 P _1 .5V S _FB _1 0 2 1 _1 .5V S _FB JP _ 10 P 6 5 3 2,37 ,45 ,4 8,5 0 S US B _ON P JP 2 1 2 1 +1.5V S S HORT_ P IN /X
1 MOHM
1 0UF/6 .3 V
8 .6 6K Oh m
P C10 6
P R11 2
P C10 4 0 .1 UF/16 V /X
P C10 5
P R11 3
P C10 7 1 0UF/6 .3 V
1 1
P T 30 P T 29
1 0UF/6 .3 V
GND
GND
GND
GND
P _1 .5V S _OV # _1 0 D
1 00 KOh m
2 S
P C12 7 0 .1 UF/16 V /X
GND
GND
2
GND
c) Switching circuit
PR93 P_VCCP_ENF_10 2 0Oh m /X PR95 820KOh m 1 1 +5VS P_VCCP_IN_S
P_VCCP_TON_1 0 P_VCCP_EN_1 0
+3VS
+5VS
P_VCCP_IN_S 2
8 7 6 5 D
GND
S G
GND
GND PU8A
17 16 15 14 13
+VCCP / 5.5A
PL13 1 2.2UH
2
1 1
PT 20 PT 21
PR96 100KOh m +VCCP 1 P_VCCP_VDD_10 2 VOUT P_VCCP_FB_10 3 VDD P_VCCP_PW RGD_10 FB 4 PGOOD
1 2
PD14 1 2
PC92 0.1UF/25V 2 1
PQ24 EMB20N03V
1 P_VCCP_SNU_S 2 1
7,42 VCCP_PWRGD
1
P_VCCP_PHASE_20 1 P_VCCP_OCR_10 2
4 3 2 1
P_VCCP_PHASE_S 1
5
2
1 1 1
+VCCP
PR98 10KOhm 1%
P_VCCP_FB_ 10
PC96 0.1UF/16V /X
1UF/16V
2
PC94
8 7 6 5 D
PR99
P_VCCP_FB_ 10 1
PR100 1Oh m
402KOh m
1
SHORT _PIN /X
5 6 7 8
GND
GND
GND
GND
4 3 2 1
GND P_VCCP_FBJP_10
1
PR101 2.74KOhm 1%
PC98 0.1UF/16V 18 20
GND 1
6
PT 37
S0
GND
UM6K1N
1
S3/S5
S3/S5
3
+5VA
GND
P_VCCP_EN_10
6
PQ62 0A 2 UM6K1N
1
PR106
PC173 0.1UF/16V /X
EN
GND
GND
GND GND
The basic principle of DC-DC switching circuit is to regulate the output voltage value by controlling the duty cycle.
Vdriver+Vboot
UGATE:
Ton
Vdriver
LGATE: Vin
Switchings advantages compared to Linear 1.Output voltage can be lower 2. High conversion efficiency
PHASE:
e) Power Latch
P R12 8 A C_B A T _S Y S 1 2 10 K Ohm
+3V_P L
20 mil
+3 V _P L
P_ 3VPL _FB_ 10
P R12 9 33 0K OHM
When insert battery only,+3VA_PL is high,3VA & 5VA will be latched low.
RT8205CGQW
+3V A +3V _P L +VCC_ RTC P _+3V A _ +5 V A_ E N_1 0 3 4
PC1 22 2 1
10 UF/6 .3 V
P U11 A P L4 31 LB A C
EN
P R13 0 20 0K Oh m
/X
P RN61 B 1 00 KOh m
P R13 1 0 Oh m /X
P RN61 A 1 00 KOh m 2
P Q37 A UM6K 1 N
+3VA
GND
P R13 2 0 Oh m
P D15 1 2 3 1 B A T 54 A W P D16 B A T 54 A W 2 1 3
GND
EC
Latch
5 P S -ON P RN61 C 6 5 1 00 KOh m P RN61 D 8 7 1 00 KOh m BAT GND P R13 4 2 P R13 6 5 10 KOh m /X 1 1 00 KOh m /X P C12 5 2 1 0 .2 2UF/2 5V/X P S -ON 32
P C12 3 0 .1 UF/16 V /X
29
P W R_ S W#
P Q37 B UM6K 1 N
GND 3 5 HOT K EY _ S W0 #_ P
When push the power button, or insert adaptor, 3VA & 5VA will exist
GND
P C12 4 2 1 1 UF/25 V /X
P R13 3 2 1 1 00 KOh m /X
A /D_DOCK _IN
P Q38 B UM6K 1 N /X 5
GND
GND
GND
Power on Test
IC VCCENABLE voltage
2. Measure the resistance between Gate and Source. If it isnt above K magnitude, the MOSFET is considered bad.
Attentions:
1.Please discharge the MOSFET before measurement (mustnt power on) : separately short G and S, G and D, D and S one time. (short G and S is necessary) 2.Measurement sequence: measure D,S or G,D first, G,S last
Summary
If MOS G-S, G-D resistance is above 1K ohm ,for high side
MOS D-S above 50ohm or for low side MOS D-S not short, the MOSFET is OK. Resistance measurement sequence: D-S, G-D, G-S Able to use diode level( and D, above 0.1V is OK. The MOS which removed should be confirmed burned or not. If all MOS is changed OK, but output still short, maybe its the problem of IC, or the load device (for Vcore or charger or any other without short pin).
1
PU500
17 16 15 14 13
RT8202APQW
5 6 7 8
1.Change good IC, check whether output is normal after power on again. 2.If abnormal, check whether the voltage of IC ENABLE and VCC pins is normal (can compare with a good one) . 3. When ENABLE is abnormal, disconnect timing control circuit, check timing control circuit after power on 4.When VCC is abnormal, measure whether the series connected resistors and VCC power rail are OK or not.
12 11 10 9
LDO circuits include +3VA,+VTT_DDR, +2.5VS,+1.5VS Firstly, measure whether output resistance is short or not . Then power on, measure each PIN voltage. Check whether input VIN, VCC, EN/SHDN# is normal to exclude timing problem. Also can check REFIN/SET/FB. Normally, correct REFIN/SET/FB voltage means IC is OK. Last, change IC to exclude the problem of IC self.
Agenda
Power Solution Introduction Common Bug Criteria and Solution
Power Solution
Power flow
Power Schematic
Always Power
Power Rail Control
EX:3VA,5VA /X (*)
Standby Power
EX:3VSUS,5VSUS VSUS_ON
Dual Power
EX:1.5V SUSC_ON
Main Power
EX:3VS,5VS SUSB_ON EX:VCCP VCORE CPU_VRON
(*):Because of the power latch circuit, theres no always power when only insert battery.
2.Power flow
BAT Adaptor
40W(1 9V/2.1A)
A/D_DOCK_IN
AC_BAT_SYS
EMB24 B03G
BAT
3S2P/ 12.6V/3A
P_AC_ARP_UC_10
AC_BAT_SYS
RT8206*1/2
H:F DMC8 884
CHG_EN# VSUS_ON
+3VSUS
CHARGER
+3VS
FDMC8 884 APL53 25
+3VSUS (5A)
(4.765A)
+5VA
+3VA
(0.1A)
+1.8VS (2.1A ) EC
VSUS_ON SUSB_ON
MP224 9
RT8206*1/2 H:FDMC8884
+5VSYS_EN
+5VSYS
VSUS_ON
SUSC_ON
L:EMB09N03V
+5VSUS&5VSUS_USB (3.3A)
FDMC8 884
SUSB_ON VSUS_PWRGD
SUSB_ON
CPU_VRON
+5VS&+5VS_USB(4.83A)
FDMC8 884
VSUS_PWRGD
VSUS_ON VRM_PWRGD
+1.1VSUS
1.1VSUS_PWRGD SUSB_ON
EMB09 N03V
+3VS AC_OK
RT8202
VSD VSC SUSC_ON
+1.5V
+1.5V
(8.15A)
H:EMB09N03V L:EMB09N03V*2
SUSB_ON
PM_DPRSLPVR
FDMC8 884
SYSTEM
+1.5VS (1.05A)
CPU
PSI# SUSB_ON
UP771 3
+0.75VS (1A)
CLK_EN#
VDDCR_NB VDDCR_CPU
(10A) (11A)
VDDCR_CPU_SENSE,VDDCR_NB_SENSE,VSS_SENSE,HT_CPU_PWRGD
+1.8VS (2.1A )
MP224 9
3.Power Schematic
Load Switch
Linear circuit
Switching circuit
Charger circuit
Power Latch circuit
a) Load switch
5VSYS_USB EN
b) Linear circuit
Mp2249: Enable >1.8V Vout begin to climb Whem Enable<0.4V will close IC
Saturation
Cut off
B D
ID(A)
2.2 2.0 1.8
Ohmic region
A Off
Saturation region
On
Off
VGS=VT+4V
VGS=VT+3V
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.22 0.1 1 1.1 1.2 1.3 1.4 1.5 1.6
VGS=VT+2V
C D B
VGS=VT+1V
VGS=VT
1.7A 1.8
1.9
2.0
2.1
2.2
VDS(V)
Output characteristic
c) Switching circuit---SYSTEM
The basic principle of DC-DC switching circuit is to regulate the output voltage value by controlling the duty cycle.
Vdriver+Vboot
UGATE:
Ton
Vdriver
Switchings advantages compared to Linear 1.Output voltage can be lower 2. High conversion efficiency
RT8206 introduce
Pin
1 2 3 4 5 6 7 8 9 10 30 11 32 12 31 13 28
Description
REF: provide 2V reference TON: Step switching frequency VCC: Power ENLDO: Contrao 19V transform5VA of LDO with EN NC VIN: provide switching of input LDO: 5VA pin out NC BYP: provide 5VA,5VSUS transform when 5VSUS OK after. VOUT1\2: 3VSUS 5VSYS PIN out FB1\2: Two switching of feedback ILIMIT1\2Two switching of OCP protect PGOOD1\2: When VOUT reach92.5% Open drain; <7.5% low
Pin
14 27 15 26 16 25 17 24 18 23 19 20 21 22 29
Description
EN1\2: >0.8V IC begin work. UGATE1\2: switching up Gate voltage PHASE1\2: switching phasevoltage BOOT1\2: Switching Boot pin LGATE1\2: switching Low gateoltage PVCC: MOSFET gate driver power supply SECFB:5VSUS->12VSUS charge pump GND PGND SKIP#: switching mode choose
d) VCORE circuit
RT8870 introduce
Pin
1 2 3 4 5
Description
RBIAS: : provide 2V reference EN: >2V IC begin work<0.8V close IC SVC: serial VID clock signal SVD: serial VID data signal PWROK:<0.57V SVI no work,>0.8V to receive SVI command
Pin
15 34 16 24 28 17 25 27 18 23 29 19 22 30 20 21 31 26
Description
RGND\NB: remote sense GND PGND_NB\0\1: L-S GND LGATE_NB\0\1: switching Low gate voltage PHASE_NB\0\1: switching hase voltage UGATE_NB\0\1: switching up Gate voltage BOOT_NB\0\1: switching boot voltage PVCC: MOSFET gate driver power supply ISP1,ISN1:return circuit of electric current ISP0,ISN0:return circuit of electric current
PGOOD: VOUT OK after open drain, voltage level decision the pull high voltage
DRPSEL: next page OCSET_NB\OCSET: Provide over current protect VCC: controller power supply FB_NB\FB: output voltage feedback COMP_NB: switching regulator error amplifier output pin TON_NB\TONStep switching frequency ISP_NBISN_NB:return circuit of electric current
7 8 40 9 10 39 11 38 12 37
32 33
35 36
13 14
e) Charger
When use adapter When use battery only
Vin Vout
CHG_EN#
EC
SMB1_CLK SMB1_DATA
MB39A132
Any of these signals not correct will cause charger works in wrong way.
e) Power Latch
When push the power button, or insert adaptor, 3VA & 5VA will exist When insert battery only,+3V_PL is high,3VA & 5VA will be latched low.
f) Power limit
When the systematic consumption reaches the Adapter consumption, Charger IC will be reduced charged the electric current to protect adapter first, if systematic consumption increase still, Power limit can work and send out PWRLIMIT#x signal to system then to drop frequently .
2. Measure the resistance between Gate and Source. If it isnt above K magnitude, the MOSFET is considered bad.
Attentions:
1.Please discharge the MOSFET before measurement (mustnt power on) : separately short G and S, G and D, D and S one time. (short G and S is necessary) 2.Measurement sequence: measure D,S or G,D first, G,S last
Summary
If MOS G-S, G-D resistance is above 1K ohm ,for high side
MOS D-S above 50ohm or for low side MOS D-S not short, the MOSFET is OK. Resistance measurement sequence: D-S, G-D, G-S Able to use diode level( and D, above 0.1V is OK. The MOS which removed should be confirmed burned or not.
1
If all MOS is changed OK, but output still short, maybe its the
problem of IC, or the load device (for Vcore or charger or any other without short pin).
1 2 3 4
PU500
17 16 15 14 13
4.How to determine whether IC is OK If there is no voltage after power on with all MOS
VOUT VDD FB PGOOD
b. Power on test
1.Change good IC, check whether output is normal after power on again.
RT8202APQW
5 6 7 8
2.If abnormal, check whether the voltage of IC ENABLE and VCC pins is normal (can compare with a good one) . 3. When ENABLE is abnormal, disconnect timing control circuit, check timing control circuit after power on 4.When VCC is abnormal, measure whether the series connected resistors and VCC power rail are OK or not.
12 11 10 9
Overview
Introduction Diagram Signal Description Repair Flow Chart Q & A (Repair Experience)
Introduction
Battery Pack: -Battery cell -Protection Board Protection circuit Gas Gauge IC : BQ2060H BQ20Z90 -Outer Casing
Rechargeable Battery
Li-Ion Battery NiMH Battery NiCad Battery
Li-Ion 90 3.6 1000 6%/month Ni-Cad 40 1.2 1000 15%/month Ni-MH 60 1.2 800 20%/month
Energy Density (W-Hr/Kg) Operating Voltage Lifetime (approx. cycles) Self Discharge
C.V. C.C.
Glossary #1
Nominal Capacity: - mAH ex: 400mAH = 0.4AH (1A= 103mA) - AH Nominal voltage: - Ni-MH : 1.2v/cell - Li-Ion : 3.6v/cell (or 3.7v/cell)
Glossary #2
Series & Parallel:
Series
Parallel
Glossary #3
Over discharge -for battery spec. (ex:3.6v Li-Ion, over discharge: under 2.75v~2.5v /cell) Over charge -for battery spec. (ex:3.6v Li-Ion, 4.3v ~4.35v /cell) Self discharge Cycle life -500~1000 (fullemptyfull)
Battery Label
Connecter(Old)
1
Pin
1 2 3
2 3456
Description
Ground Battery Type HDQ Bus I I/O
Signal
GND TS HDQ_BAT
Type
4 5
6
BAT_EDV NC
BAT_S
I
PWR(I/O)
Connecter(New)
Battery Pack
Battery connecter
PIC16C54
HDQ Bus
HDQ
BQ2050H
2 3456
Battery Learning
Charge Full Discharge NAC=0 (Discharge complete) Charge Full
FRAME
FRAME
FRAME
AC_APR_UC
PKPRES#
2200mAh 2600mAh 2800mAh 6cell 47.520Wh 56.160Wh 60.480Wh 8cell 63.360Wh 74.880Wh 80.640Wh
EC
EC
OK
Trace the related circuit, Change NG related Component/fix any trace open
NG
OK
Finish
charger MB39A132
1Adapter/battery transform
Charge IC
Only adapter, insert an instant spike CAP absorbed by the system side; AC_BAT_SYS = A / D_DOCK_IN, PQ8903 not conduct, Adapter to the system power supply; ACOK down after, PQ8902 fully on;
Only battery, PQ8902 off, PQ8903 conduction, Battery power supply to the system Adapter, Battery are the presence, PQ8902 turn, PQ8903 off, Adapter power supply to the system, while to the Battery Charge; charge IC with current share function, when the system current increases, charging the charge current will decrease.
2Prepare charge
BATSEL_1 BATSEL_0 VSET_EC ISET_EC CHG_EN
AC_IN_OC# ACOK
MB39A132
Pack
EC
TS1#
BAT1_IN_OC#
Battery DETECT
Adaptor DETECT
adapter in detect
ACOK=13.7V/17.4V Adapter present ACOK=Low AC_IN_OC#= Low Adapter absence ACOK=High AC_IN_OC#= High
Battery in detect
Battery present
TS1#=LowBAT1_IN_OC#=Low
Battery absence TS1#=HighBAT1_IN_OC#=High Note:Have project directly TS1 # and BAT1_IN_OC # to short
SMB0_CLK SMB0_DAT
MB39A132
Battery Pack
EC
TS1#
BAT1_IN_OC#
Battery DETECT
Adaptor DETECT
Smart charging EC control the VCHG & ICHG Model Share the circuit Support 2S/3S/4S battery
VSET_ECEC according to the information of battery, and set the charge voltage of single cell. ISET_ECEC according to the related number of battery and battery status (Pre-charging or Quick-charging) to set voltage electric current CHG_EN When BATSEL_0 BATSEL_1 VSET_EC ISET_EC setting finished, put CHG_EN to High and start charging.
BATSEL_0 BATSEL_1
BATSEL_0 BATSEL_1EC according to the series connection number, notify the charge IC and according to the VSET_EC message to set Battery charge voltage.
Pack
EC
MAX8725
TS1#
BAT1_IN_OC# AC_IN_OC# CHG_AC_OK
Battery DETECT
Adaptor DETECT
BATSEL_2P#Ec tell Charge IC about batterys pack Set CC BATSEL_2P# =Lowis a 2P/3P batteryICC=2.5A BATSEL_2P# =Highis a 1P batteryICC=1.5A PRECHGEC detect the Battery Voltage <3V*CellsPRECHG=1 Battery-Pack into the Pre-Charging Modecharge current=150mA CHG_EN#EC detect the Battery ,when it reach the condition of charging CHG_EN# = 1, Charger Disabled; CHG_EN# = 0, Charger Enabled
VSET_EC ISET_CTL
MAX17015
Pack
EC
AC_IN_OC# CHG_AC_OK
TS1#
BAT1_IN_OC#
Battery DETECT
Adaptor DETECT
Smart charging EC control the VCHG & ICHG Model Share the circuit Support 2S/3S/4S battery
VSET_ECEC according to the information of battery, and set the charge voltage of single cell.
ISET_ECEC according to the related number of battery and battery status (Pre-charging or Quick-charging) to set voltage electric current
CHG_EN When BATSEL_0 BATSEL_1 VSET_EC ISET_EC setting finished, put CHG_EN to High and start charging.
d) Charger
A /D_ DOCK_ IN 1 P R35 15 mOh m 2
A C_B A T _S Y S
6
D2
P C30 47 00 P F/5 0V
1
P C31 0.1 UF/25 V
P Q8 E MB 24 B0 3G
D1
D1
D2
P R36
G1 S1 S2 G2
GND
P_CHG_AIRS+_ 5
P_CHG_AIRS-_5
23
P T 25
P _CHG_P HA S E _2 0
2 S
/X P C35 1
P C33 10 UF/2 5V
4 3 2 1
GND
2 6.8 UH
2 25 mOHM
P C39 1UF/16 V
P D8 /X B A T 54 CW
GND P R44 20 0K Oh m 1 2 3 4 5 6 7 8
33 32 31 30 29 28 27 26 25
CHG_V CC GND V IN CT L1 GND1 V RE F RT CS A DJ3 BAT T 24 23 22 21 20 19 18 17 P _CHG_V IN_1 0 P _CHG_CT L 1_ CTL 2_ 10 P _CHG_RT _ 10 P _CHG_CS _ 10 P _CHG_A DJ CV_ 10 P _CHG_V B T T _1 0 MB 39 A 13 2_ VRE F P Q13 E MB 20 N0 3V
P C40 10 00 P F/5 0V
P C41 10 UF/2 5V
1
GND
ACIN
P Q10 B UM6K 1 N 32 B A T _L EA RN 5
1 CHG_COMPAI_1 0
P R46 22 K Ohm
P R43 22 0K Oh m
P _CHG_L G_2 0
4 3 2 1
P R49 10 0K Oh m 2 GND
1UF/25 V
P U3A MB 39 A 13 2
P C44
P R48 33 K Ohm
GND
GND
+3 V A GNDGND 2 P R51 22 K Ohm 1 2 P C49 82 0P F/50 V 2 1 1 P C51 /X 12 0P F/50 V 1 P R56 10 K Ohm P _CHG_INE 3-_ 10 GND GND +5 V S US
GND
GND
P R52 56 K Ohm
P R53 10 K Ohm 1% /X
12
P R54 10 0K Oh m
GND
T P C26 T P T 15 /X 2
P C53 10 00 P F/5 0V
CHG_E N#
32
P RN62 B 10 0K Oh m
P T 26
CHG_EN#
P Q15 3 2N7 00 2 11
11 G 2 S
32
P RN62 CS 2
P RN62 D 10 0K Oh m
UP 62 68 A MA 6
32 ,38 S MB 1_ CL K 32 ,38 S MB 1_ DA T A
1 2 3
6 5 4
38 ,43
10 0K Oh m
P U4
/X
GND
10 0K Oh m
P_ADIN_ SNU_S
V mi d
1 2 3 4
8 7 6 5
BAT
P Q9 E MB 20 P0 3G
2 P _CHG_A COK #_ 10
Vin
A C_B A T _S Y S
P _A C_ AP R_ UC_ 10
11
GND
P Q12 E MB 20 N0 3V
8 7 6 5 D S G
Vout
BAT P C42 10 UF/2 5V
P_CHG_SNU_ S
8 7 6 5 D S G
P JP 1 0/X S HORT _ P IN
P JP 1 1/X S HORT _ P IN
P JP 1 2/X S HORT _ P IN
Battery present: BAT_IN=high; Battery absent: BAT_IN=low. Adapter present: AC_OK = high; Adapter absent: AC_OK = low; CHG_EN# = low, Charger Enable CHG_EN# = high, Charger Disable Battery Package
BAT_IN# SMB1_CLK SMB1_DATA CHG_EN# AC_OK
EC
SMB1_CLK SMB1_DATA
MB39A132
Any of these signals not correct will cause charger works in wrong way.
Overview
Diagram Signal Description Repair Flow Chart Repair Technique Q & A (Repair Experience)
-1
CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK# CLK_REQ_MCH# CLK_MCH66 (AGP/Hub-link) CLK_MCH_3GPLL (PCI-E x16 /with DMI-link) CLK_MCH_3GPLL# (PCI-E x16/with DMI-link) DREFCLK (for GMCH) DREFCLK# (for GMCH) CLK_AGP66 (AGP) CLK_PCIE_PEG (PCI-E) CLK_PCIE_PEG# (PCI-E) CLK_VGA27 CLK_ICHPCI CLK_USB48 CLK_ICH14 CLK_ICHHUB CLK_PCIE_ICH (PCIE x1) CLK_PCIE_ICH# (PCIE x1)
CPU
MCH
(Hub/DMI) (PCI-E) (GMCH)
VGA
(AGP/PCI-E)
ICH
(HUB) (PCI-E)
-2
CLK_CBPCI CLK_MINIPCI CLK_LANPCI CLK_SIOPCI
CLK_SIO_14M
CLK_KBCPCI CLK_FWHPCI CLK_PCIE_NEWCARD
NEWCARD
MINICARD
SMB_CLK SMB_CLK
Xtal 14.318MHz
52 51 44 43 40 19 20 14 15 9 12 60 39 38 5 8 3 64 4
CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK# CLK_REQ_MCH# CLK_MCH_3GPLL CLK_MCH_3GPLL# DREFCLK DREFCLK# CLK_ICHPCI CLK_USB48 CLK_ICH14 CLK_PCIE_ICH CLK_PCIE_ICH# CLK_CBPCI CLK_LANPCI CLK_KBCPCI CLK_TPMPCI CLK_FWHPCI
Yonah-CPU
(Dual Core)
16
Calistoga GMCH
(945GM)
ICH7-M
CARDBUS R5C832 KBC M38857
VTT_PWRGD# 10
1 2
57 58
Xtal 14.318MHz
FWH 49LF004A
CBPCICARDBUS 33 MHz LANPCILAN 33 MHz KBCPCIKBC 33 MHz TPMPCITPM 33 MHz FWHPCIFWH 33 MHz
CLK_PCIE_MINICARD/MINICARD# CLK_REQ_MINICARD#
MINICARD NEWCARD
22 23
CLK_PCIE_NEWCARD/NEWCARD# CLK_REQ_NEWCARD#
44 43 35 34
CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK# CLK_MCH_3GPLL CLK_MCH_3GPLL# DREFCLK DREFCLK# CLK_ICHPCI CLK_USB48 CLK_ICH14 CLK_PCIE_ICH CLK_PCIE_ICH# CLK_CBPCI CLK_LANPCI CLK_MINIPCI CLK_KBCPCI CLK_FWHPCI
VTT_PWRGD#
16
32 31 14 15
9 11 53 25 26 56
FSLC
ICH6-M
CARDBUS R5C841 MINIPCI (WLAN) KBC M38857 FWH 49LF004A
CBPCICARDBUS 33 MHz
1 2
49 50 2,6,12,30 38,45,51
54 55 3 4
MINIPCI for WLAN Card 33 MHz KBCPCI for Keyboard ler 33 MHz FWHPCI for BIOS CLK 33 MHz
Xtal 14.318MHz
Frequency Programming
ICS954213-Block
Pin (1)
Pin (2)
ICS954310-Block
Pin (1)
Pin (2)
Pin (3)
Ordering Information
Finish
To check Clock Generator and Xtal and related components are not damaged.
Fix any trace open & BAD solder problem.
1
Xtal 14.318MHz
CLK Gen.
Xtal CLK=14.318MHz
3-2
Ps: (when press power bottom the VTT_PWRGD# signal status is from 3.3V0V)
VTT_PWRGD#
4-1
Overview
Connector Pin Definition Block diagram Schematic Debug Tips
DDC/CEC GND
+5V Power Hot Plug Detect
Block diagram
With level shifter
MB
+3Vs
PCH
TMDS CLOCK
DDC CLK/DAT
Level Shifter
TMDS CLOCK
DDC CLK/DAT
HDMI connector
Schematic
HDMI conn.
Level shifter
Overview
Diagram Theorem Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram
+5V
+3V
LPC
SB
KBC
CLK_KBCPCI
XTAL
33MHz
8MHZ
Circuit
KBC
CONNECT
Change Defect Connector & OK damaged RLC components NG Be sure the function is no disable in O.S NG Check KBC Voltage & CLK, +3V , CLK_KBCPCI = 33MHz Xtal = 8MHz . Check T/P Connector Voltage, +5V Trace circuit, Change NG Component and fix any trace open NG OK OK
Finish
CID
2-2
+3V is ok.
3-2
4-2
If the problem is still existing, please change Touch Pad Controller K/B Chip
PIN1,2,3,4,5,6
6
1 2
3
4 5 6
INDTATA_5S
INTCLK_5S GND GND
602
602 0 0
metal
Top-Top Top_Bottom
When the button is going down, the signal reveals the normal response
Overview
Diagram Circuit Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram-1
+3V
KSO0 ~KSO15 KSI0 ~ KSI7 KEYBOARD CONNECTOR
Keyboard control IC
Ex: M38857M8
LPC
SB
XTAL
CLK_KBCPCI
8MHZ
KEYDETECT1 KEYDETECT2
33MHz
Array resistor
+3VS
Diagram-2
Embedded Keyboard controller -Matrix
PS : Maybe there is no Super IO in new NPI model, because there are no PS/2 Port, COM Port or Print Port etc. on those model.
Diagram-2
Circuit-W6A
Circuit-W6A
OK
OK
Finish
If V.I check is OK, and problem still is exit. Please change New one K/B to Test at first.
1-2
If the problem is still existing please change S.I.O (super I/O) controller.
1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~24
W6A K/B
26
28~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
KSI is nature Pull high 3.3V KSO design is Open Drain need pull High by outside
Key Board
Overview
Diagram Signal Description Theorem Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram(1)
AC97
Pin1,Pin9 : Pin2,Pin3 : +3VS_Code 24.576MHz
Speaker
SB
AD1885
Speaker
5-pin serial data transaction : (1) BIT_CLK (2) SYNC (3) RESET (4) SDATA_IN (5) SDATA_OUT
Pin25,Pin38,Pin43 : +5VS_AUDIO
Diagram(2)
Azalia
Pin1,Pin9 : +3VS_Code
Internal Speaker
SB
ALC880
External Speaker
(1) BIT_CLK (2) SYNC (3) RESET (4) SDATA_IN (5) SDATA_OUT
Pin25,Pin38 : +5VS_AUDIO
ALC663
Pin Assignment-(HD-ALC269)
Signal Description-1(HD-ALC269)
Signal Description-2(HD-ALC269)
Signal Description-3(HD-ALC269)
Pin Assignment-(HD-ALC663)
Signal Description-1(HD-ALC663)
Signal Description-2(HD-ALC663)
Signal Description-3(HD-ALC663)
Theorem
HD link (Azalia link)
H/W Architecture
Link
Codecs
Controller
Software
ICH6
AC 97 Legacy
AC Link
Azalia ler
or
Azalia Link
pins: support up to 3 codecs 8 Independent DMA operations 4 Input, 4 output streams 24 MHz BITCLK is driven by the Intel ICH6
Dock
Dock Codec
Fix bandwidth assignment, fix slot base protocol Pre-defined DMA use age
Support for multi-streaming / multiple similar device types can be supported Support for new Digital Home / Digital Office useage models Single, high-quality, stable clock source for synchronization Single bus driver for more OS stability & base functionality Support for full audio PnP
Single stream support (in & out) Clock provided by primary codec Stability depending on SW provider (IHVs drivers) Limited device sensing / jack retasking 2-element (stereo) array mic support
Support for multiple streams (in & out) Clock provided by the Intel ICH
OK
Check Setting in the BIOS, The Audio Function must be is UNLOCK NG Measure Audio Code Voltage: +3VS_Code and +5VS_Audio Measure Audio AMP. Voltage: +5VAMP Measure Audio Code CLK: 24.576MHz (only AC97 model) Measure Audio AMP. SE/BTL# : H: for Int. SPK ; L: for Ext. SPK
OK
Fix or change any R.C.L.Q component related to Voltage NG Change any NG component related to Xtal. NG
OK
OK
OK
OK
Change S.B
Finished
NG
CID Case
OK 1-1
Broken
24,576MHZ
Audio
ALC269
To S/PDIF
Head Phone
Repair skill
General repair rule:
1. Check Software environment seting:BIOS Driver version
Make sure is the latest version and Device is lock. 2. Volume settings, mute, or if there is sound or voice pulled minimal Bar
Have the right to set the output of the device ... etc.
HP Jack &S/PDIF
Amplifier
TI----TPA3110 Class D Amplifier
INT Left Speaker Close AMP output (Mute)
AMP Power
MIC
INT or EXT MIC Schematic:
To ALC269 Codec
Repair skill
EXT MIC & Head Phone detect the way of examining
Overview
Diagram Circuit Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram
RJ-11
Azalia BUS
RESET# & SYNC TIP & RING BIT_CLK
SB
Circuit
NG
Check Modem Type (by model) OK /Change New one Modem Board NG
1.Check Power source to Modem CON. Resistor and Trace 2.Check RJ-11 TIP / RING signal
OK
OK
Finish
Visual Inspection 1.check RJ-11 connector is no Damage or Pin bend or Pin bad solder. 2.check Modem connector is no Damage or Pin bend or Pin bad solder.
1-2
3.R.L.C. components is not miss or damage 4.Check PCB trace is no open or scratch
CID
2-2
3-2
Modem Board CON. Signal Name BIT_CLK SYNC RESET# SDATA_IN SDATA_OUT Diode Value 391 Signal Name 426 391 391 391 RING OL TIP OL Diode Value RJ-11
Overview
Diagram Signal Description Theorem Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram
Signal Description
Pin Define 1 2 3 4
OK
OK
Check Fuse or Inductor and Trace Change Defect Component NG Check Resistor or Inductor and Capacitor and Trace and S.B OK Change Defect Component NG
Change S.B
Finish
1-1
1-2
2-1
Check GND
2-2
3-1
Check USBP-
3-2
Pin 1,2,3,4
2 3 4
+/- 5
USB port
HM65 has 12 USB2.0 port
USB2.0 Schematic
USB Power
GND
Pin Define 1 2 3 4 VSUS DD+ GND +5V Power Data Data Ground
Repair skill
General repair rule:
1. Check Software first: BIOS Update USB device Lock 2. Check H/W have bad or ok
USB3.0
Schematic
CLK & PCIE
POWER
If it is found external USB3.0 DEVICE can not recognize the external, may be used for confirmation
External device and cable is the normal state? Device Manager the device is abnormal?
If there is an exclamation point, to re-install the device in the OS, the driver, further confirmation. If the device can not see to open the machine to be recognized as a measurement signal can be sure the system clock is normal to provide? If the clock normal, and we have the power part of the measurement, including the device itself its own power (+3 V_USB3 / + VCC_12A), the general line on the road there will be short pad to enable us to confirm that the power system or the device.
There are problems, there is another external device provided to the power (+5 V_USB30 also need to confirm, and use the oscilloscope to confirm that the external device is plugged in, whether caused by power lost
Overview
Diagram Theorem
Diagram
+3V +5V
VCC3_EN VCC5_EN Power (R5531V002) VCC VPP
+3V
CCLK#
CRESET#
SB
PCI BUS
CAD[0:31] C#
CLK_CBPCI (33MHZ)
XTAL
24.576MHZ
Overview
Diagram Signal Description Theorem Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram
+3V
PCI Clock:33MHz
Xtal : 24.576Mhz
SB
R5C841 SMBus +3V
EEPROM
1394
Circuit
R5C841
Pin Define
R5C841
1394a Connector
6 Pin
4 Pin
1394b Connector
9 Pin
EEPROM Pinout
AT24C02N
Check 1394 setting is unlock in the BIOS. Change NG Component /Fix any trace open NG
OK
OK
OK
Change NG Component/ Fix any trace open NG Check EEPORM Voltage, +3V Change NG Component/ Fix any trace open NG
OK
OK
OK
Finished
Visual Inspection to check 1394 connector, controller & related component is not damaged. 1-1
CID
1-2
3
Measure IEEE 1394 controller voltages: (RICOH R5C841) Pin : +3V
GND
5-1 If still cannot find any abnormal please try to change 1394 controller and check other device under PCI bus. If the problem is still existing after change 1394 controller, please change SB at last.
TPB0-
TPA0-
TPB0+ TPA0+
5-2
TPB0-
TPA0-
TPB0+ TPA0+
1394_SCL 1394_SDA
Overview
Diagram Signal Description Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram
+3V
CD CMD
+VCC A
SB
PCI BUS
CLK_CBPCI (33MHZ)
XTAL
24.576MHZ
CD Card Detect CMD Comm WE# Write Enable CE# Card Enable CLK Clock PC Power WP Write Protect DA0~3 Data 0~3
Circuit-1
Circuit-2
Confirm the problem Is MMC/SD error or MS/MS-pro error Change Defect Component Measure Voltage, VCCA = +3V is OK (Control signal MCVCC3EN# is Low active) Measure clock, Check related Resister 0 ohm
Check Voltage is OK ?
Check MSCLK/SDCLK is OK ?
GND
GND
4 Check CMD
1.Use multi-meter to measure CMD Pin(23)is correct
GND
Repair Technique-DATA0~3
5 Check DATA 0~3
1.If memory type is disordered or data transfer fail please Use multi-meter to measure DATA0~ 3 Pin13 -> DATA0 Pin11 -> DATA1 Pin27 -> DATA2 Pin25 -> DATA3
GND
GND
23
24 25 26 27 28
SDCMD
SDCLK/MSCLK SDDATA3 VCCA SDDATA2 GND
496
492 498 596 498 0
11 12
13
9 28 14 15 16
SDDATA0
VCCA GND SMCD2
497
596 0 503
Card Reader
AU6433
USB Interface
To Connector
CR Schematic
48Mhz Clock to PCH
POWER
Repair Skill
Check BIOS is locked or not, driver is updated to the latest version. 2.Check Connector have dirt or bad connection => AU6433 IC How to check AU6433 IC is normally
Each POWERs voltage levels CLOCK voltage levels and frquence
Chip Reset pin pusj to HIGH to 3.3Volt
Overview
Diagram Theorem Q & A (Repair Experience)
Diagram
Clock GEN
CLK_SATA_ICH
SATA HDD
SATA BUS
SB
Circuit
SATA HDD
South Bridge
ODD&HDD
HM65 has total 6 SATA ports
2 SATA 6 Gb/s (port 01) 4 SATA 3 Gb/s (port 2345)
SATA Port0
SATA Port2
SATA HDD
SATA ODD
HDD Schematic
To PCH
+5V POWER
Finish
Chapter 15
Diagram Theorem Repair Flow Chart Q & A (Repair Experience)
Diagram
Clock GEN
CLK_SATA_ICH
S.B
SB
Circuit
ODD Schematic
+5V POWER POWER Enable Low Active
To PCH
ZPODD Introduction
Zero Power ODD (ZPODD): When the ODD idle will automatically power off until the user to use the ODD, it will power on the mechanism Required with BIOS, ODD, and MB H / W can be Support
Default idle 1min after the power was automatically cut
CD-ROM disc or a disc out within the ODD does not cut
power.
Repair Skill
1.Check BIOS have Lock ODD, BIOS is updated to the latest version, SATA Controller Driver for updates to the latest version.
Introduction
SATA Controller driver
OK
Use multi-meter to measure ODD signals diode value, compare with good MB.
Change S.B
Finished
Overview
Diagram Signal Description Theorem Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram
+2.5V_LAN +3V_LAN PCI_Reset #
Clock :
1.25MHz
2.CLK_LANPCI
PCI_BUS
SB
LAN IC
Transformer 10/100MB
RTL 8100CL
SMBus
+3V_LAN
EEPROM
Diagram
93C46
Change Defect Connector/Component Can Write LAN ID ? Fail LAN ID Error NG Check Lan Voltage, +3V_LAN,+2.5V_LAN Confirm the circuit, Change Defect connection R,L,C or Transistor Components. NG OK Re-write LAN ID Address /Load BIOS default
OK
OK
OK
OK
OK
OK
NG
OK
OK
Finish
Visual Inspection to check 1.LAN(RJ-45) Connector/Pin is OK. 2.Related components is no miss and damage or burned
1-1
CID
1-2
LAN MAC ID
3 Check LAN MAC ID address is correct/available (Not 000000 000000) If LAN MAC ID fail, Please Re-write LAN MAC address first. If the problem still exist, check Voltage is OK and then use multi-meter to measure diode value of EEPROM
4-1
2: +2.5V_LAN
LAN IC
93C46
Some signals should be connected together (Show as Fig.5-2, the signals marked Green color) If Transformer NG, please change it . 5-1
TDP TDN
LAN_TX+ LAN_TX-
RDP RDN
LAN_RX+ LAN_RX-
5-2
6-1
TDP TDN
LAN_TX+ LAN_TX-
RDP RDN
LAN_RX+ LAN_RX-
6-2
93C46
Overview
Diagram Signal Description Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram
+3VS
RED
PIN1
PIN2
NB
GREEN
PIN3
BLUE
+12VS
Signal Description
1 6 11 ~ 5 10 ~ 15
Check Voltage is OK ?
OK
Finish
1-1
Visual Inspection:
1.check VGA connector is no damaged and bend.
1-2
CID
3-1
Check the problem belongs to (i) RGB color error problem (ii) No display or display error problem.
test point
(i)
RGB color error problem please use multi-meter to measure which color (R.G.B.) signal is error. Trace the connection to confirm related inductor or capacitor is ok. If its not caused by R.L.C.Q. small components please change NB or Graphics Chip.
Pin 15,4,9,13,2,7,11
(ii) No display or display error (not included color error). Use the meter to measure Diode value on DDCCL &DDCDA, VSYNC & HSYNC. Trace the connection to confirm related R.C.L.Q. is ok. If all check items are no problem please change NB or Graphics Chip
Pin 5,10,14,3,8,12,1,6
Pin 15,4,9,13,2,7,11
R/G/B out
(37.5ohm) (trace imp.) (50ohm) (trace imp.)
Monitor
PCH
150ohm 150ohm 75ohm
Analog RGB
Sync
DDC
Block diagram
MB
RGB
PCH
DDC CLK/DAT
PIN
Description
RED
GREEN BLUE NC GND GND-R GND-G GND-B NC
VGA_HSYNC VGA_VSYNC
2 3 4
D-sub connector
5 6 7 8 9
10
11 12 13 14 15
GND
NC DDC DATA H-Sync V-Sync DDC CLOCK
Schematic
DDC
D_SUB Conn.
Debug Tips
Common issues:
CRT can not be detected (Fn+F8 cannot find the monitor) Exchange monitor to verify Check resistance:
RGB connector side (with monitor): 37.5ohm RGB connector side (without monitor): 75ohm
Abnormal / No display Check PCH DAC power VccADAC Check RGB/Hsync/Vsync connection and related components (buffer IC, beads, PCH)
Screen blinking Hsync/Vsync Overall color abnormal RGB
Overview
Diagram Signal Description Theorem Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram-1
System Board Side
+3Vs Display panel GMCH
LCD_ENVDD
LVDS FFC
LVDS Bus
LCD_ENBACK LCD_BACK_ADJ ADJ_BL
LVDS
BACK_OFF#
LID_RSM#
Cable
Inverter Board
Inverter board
SB
KBC
LID Switch
AC_BAT_SYS
Diagram-2
System Board Side
+3Vs ATI VGA AGP Bus/ PCI-Express
LCD_ENVDD
LVDS
LVDS Bus LVDS
FFC
MCH
ADJ_BL BACK_OFF#
LCD_ENBACK
Cable
LID_RSM#
SB
KBC
LID Switch
AC_BAT_SYS
Circuit-1
GMCH
Circuit-2
LVDS
Circuit-3
Inverter board
Signal Define-1
Signal Define-2
Signal Define-3
OK
1.Clear CMOS and Load Default 2.Check Fn + F5 or F6.etc. (depend on model request) NG
OK
2
Finish
1.Check BACK_OFF# , Voltage = 3V (from S.B) 2.Check LCD_ENBACK , Voltage = 3V (from N.B or Graphic) 3.Check LID_RSM# , Voltage = 3V 4.Check KBC ADJ_BL , Voltage = between 0~3V (from KBC) (depend on model different)
Trace the related circuit, Change any NG related RLC Component and control IC
NG
OK
Finish
Check LVDS Voltage LCD_VCC, LCD_VCC =+3V And check control signal voltage, LCD_ENVDD = +3V (signal from NB or Graphic IC)
Trace LCD_VCC signals related circuit, Change NG RLC and MOSIC Component
NG
OK
Check LVDS Voltage ( GMCH / Gfx ), +2.5V Check VGA Core Voltage ( GMCH / Gfx ), +1.5V or +1.05V / ATi_Vcore 1.0~1.2V (depend on RD design request) AGP / PCI-E: Check LVDS Clock for GMCH, 1.DREFCLK(#) 48MHz 2.DREFCLK(#) 96MHz Check LVDS Clock for Gfx, 1.CLK_MCH66/AGP66 66MHz 2.CLK_PCIE_PEG(#) 100MHz Check LVDS Data, LADATAP[0:2] & LADATAN[0:2] Check LVDS Clock, LACLKP & LACLKN
OK
Measure Clock
Change any NG RLC Component or CLK Gen./ Fix any trace open
NG
OK
OK
Finish
Inverter
1-1
CID
1-2
2-1
2-2
+
3-1
+
3-2
4-2
7-2
96MHz
LVDS basics
LVDS (Low-voltage differential signaling )
Small current (3.5mA) through 100ohm +/-350mV
Block diagram
MB
+3Vs
LCD panel
LVDS
PCH
EDID CLK/DAT
L_BKLTCTL L_VDD_EN L_BKLTEN
Cable
LCD connector
LID_SW#
EC
LID Switch
AC_BAT_SYS
Schematic (1)
+LED_VCC:
LED power supply (7~20V)
+3VS_LCD:
LVDS 3.3V power
Schematic (2)
BUF_PLT_RST#:
Platform reset signal from PCH
LCD_BACKEN_PCH:
BL enable from PCH
LCD_BACKOFF#:
BL enable from EC
LID_SW#:
LID switch from HALL sensor IC
L_BKLTCTL_PCH:
BL PWM control signal from PCH
L_VDDEN_PCH:
LVDS 3.3V power enable
Black screen:
Check power No backlight, but display is OK (EC, PCH, LID switch) check backlight enable circuits
Overview
Diagram Signal Description Introduction Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram
+3VS
Clock Gen.
Cloc k
BIOS
SIO
SB
Circuit
Signal Description-(1)
Signal Description-(2)
Signal Description-(3)
Signal Description-(4)
Introduction
Memory Map SST 49XXX series Block Diagram Theorem
49xxx Reset-1
FWH Mode
49xxx Reset-2
PP Mode
SPI ROM
W25Q32BV:32Mbit/4MByte
You can use SPIROM BIOSs MFGID to determine XXXNAS.2XX 2MByte BIOS XXXNF1.2XX 4MByte 4M BIOS can be burnt Inside the SPIROM of 8m All right! !! But can't start the machine Because can not recognize ME FW
The signal amount is examined for SPI SI/SO at start the boot in the instant
SPI_SO
SPI_SI
Often meet the question ,user update bios to fail and not boot. CPU_RST#???
Confirm circuit of Power IC, Check Power signal VDD(+3VS) Check connection RLC/diode Components Check CLK signal CLK(33MHZ) 1.Confirm circuit of CLK Gen. Change Defect Component Change Defect Component
Finish
BIOS
1-2
Use External BIOS Boot up 1.If External BIOS can Boot up computer ,we can try to update BIOS image file first Jump Setting :
1. 2. 3. 4. on off on off --- Boot from debug card off off on off --- Boot from M/B
on off off off --- Update M/B Bios From Debug Card
2
27 VDD
25
VDD
Check VDD Voltage: Check BIOS VDD(+3VS) Voltage : Pin 1 : +3V Pin 25: +3V Pin 27: +3V Pin 32: +3V
CLK
Check CLK Frequency Check BIOS CLK Frequency: Pin 31: 33MHZ
31
DIS_SYSBIOS#
11
24 23
INIT# L#
Measure BIOS Pin signal of Diode value is normal or not? Pin 13: LAD[0] Pin 14: LAD[1]
LAD[1] LAD[2]
14 15
LAD[3]
17
LAD[0]
13
10
11 12 13
Overview
Diagram Introduction 1.DDR 2.DDRII 3.DDR3 Signal Description Repair Flow Chart Repair Technique Q & A (Repair Experience)
Diagram(1)
NB
CLK Gen.
CLK Gen.
Diagram(2)
N.B
MA0~13 MD0~63 +1.8V ( for DDR2 ) +0.9Vs ( for DDR2 ) +2.5V ( for DDR ) +1.25Vs (for DDR )
CLK Gen.
Diagram(3)
N.B
MA0~13 MD0~63
+1.5Vs ( for DDR3 )
CLK Gen.
CLK Gen.
DDR I vs DDR II
DDR3
Memory Type
200 pins
200 pins
204Pin
Micro-DIMM
172 pin
214 pin
New fearture
Dual Channel
The two channels handle memory-processing more efficiently by utilizing the theoretical bandwidth of the two modules, thus reducing system latencies, the timing delays that inherently occur with one memory module.
Matched DIMM configuration in each channel Same Density (128MB, 256MB, 512MB, etc.) Same DRAM technology (128Mb, 256Mb, or 512Mb) Same DRAM bus width (x8 or x16) All either single-sided or dual-sided
DDR2 Termination
DDR2 modules contain the require resistor termination located on the memory chips using a technique called On-Die Termination [ODT]. While DDR1 modules have the necessary resistive termination located on the motherboard. Using ODT, DDR2 are able to reduce the parts count required for mother board while at the same time locate the terminations closer the the signal destination. The ODT termination can be turned on or off by the DRAM controller. Normally the terminations are turned on for Writes and disable for Reads. The value of the ODT termination is selectable based on the number of modules in the system. With one DIMM module the ODT value is set at 150 ohms [300W pull-up and 300W pull-down]. When two modules are loaded into the system the ODT value is exchanged to 75 ohms [150W pull-up and 150W pull-down] for the DIMM not being written to while the DIMM being accessed has its ODT turned off. Writing to the Extended Mode Register [EMR] controls the ODT presence and value. Three combinations are allowed; termination disabled, 75 ohms, and 150 ohms [ also 50 ohms]. The newest revision adds 50 ohm termination values. ODT improves the eye-structure over SSTL for either Single-Rank or Dual-Rank modules.
DDR 3
DDR 3
DDR3 SDRAM(Double Data Rate Three Synchronous Dynamic Random Access Memory) DDR3 SDRAM improves on DDR2 SDRAM in several significant ways: 1.Higher bandwidth due to increased clock rate 2.Reduced power consumption due to 90nm fabrication technology 3.Pre-fetch buffer is doubled to 8 bits to further increase performance 4.The voltage of DDR3 SDRAM DIMM's was lowered from 1.8V to 1.5V. This reduces power consumption and heat generation, as well as enabling more dense memory configurations for higher capacities.
DDR 3 Top
DDR 3 Bottom
Memory
I7 CPU(2820QM2720QM) can support 2 pcs 1600Mhz DIMM. 4 pcs DIMM only support 1333Mhz DIMM.
Qual Core CPU need use A1B1 Dual Core CPU need use A0B0
Introduction
+1.5 Volt
+0.75 Volt
+0.75 Volt
Introduction
Repair skill
General repair rule:
Check the specific DIMM have problem or not. Check some slot have problems or not. Check Connector have dirt or bad soldering (using the macro mode) .Check POWER and CLOCK level and frequency If its Memory issueuse MT420 memory test program to test
Check Memory Voltage, 1.8V or 2.5V or 1.5V (depend on Memory type) Check Memory Vtt Voltage, 0.9Vs or 1.25Vs (depend on Memory type)
Fix any voltage regulator IC or related RLC component, Fix any trace open NG
OK
Confirm the circuit, Fix any trace or RLC damaged/ change NG CLK Generator NG
OK
OK
Change N.B
Finish
2.Check related resistor , capacitor component no damage. 3.Fix any trace open or BAD solder 1-1
CID
1-2
Use Multi-Meter or Oscilloscope to measure Memory Voltage & Vtt Voltage . Memory Voltage: SDRAM: 3Vs DDR :2.5V DDR2: 1.8V Memory Vtt Voltage: DDR :1.25Vs DDR2: 0.9Vs
2-1
2-2
3-1
3-2
Diode Mode
Overview
What is POST CODE Using POST Code to Debug Appendix: (1)BIOS CODE Definition (2)BIOS Beep Code Q & A (Repair Experience)
The tag thrown out by BIOS Usually, BIOS would output some number through 80ports. Using I/O access card (debug card), user could read those number. The POST codes used by Award, Phoenix, and AMI are different. These numbers mean something was executing in the system.
Standard POST Code These numbers were used as standard process. BIOS Debug Code These numbers depend on various project.
POST 00, FF
POST Code 00,FF or Debug card shows all dots() / all 00 (1)Check Voltage: a.) Vcore ,if no Vcore check from power block circuit diagram b.) 1.5v,if no 1.5v check from power block circuit diagram c.) 2.5v,if no 2.5v check from power block circuit diagram d.) 3.3v,if no 3.3v check from power block circuit diagram e.) check for N/B,S/B voltage is ok or not (2)Check CLK: a.) CPU CLK,if no CPU CLK check from CLK gen. circuit diagram b.) N/B CLK,if no N/B CLK check from CLK gen. circuit diagram c.) S/B CLK,if no S/B CLK check from CLK gen. circuit diagram d.) 14.318MHz,if no 14.318MHz check from CLK gen. circuit diagram e.) CLK generator. if all no CLK,change 14.318MHz,and then change CLK gen. Before must check any open or short
(3)Check Power ok & Reset a.) H/W reset,if low voltage check circuit diagram, normal is capacitor bad b.) power supply power ok,if low voltage,normal is capacitor bad c.) CPU power ok,if low voltage check circuit diagram,and above signal d.) PCI reset,if low voltage check above signal and for S/B CLK,voltage e.) CPU reset,if low voltage check above signal and for N/B CLK,voltage f.) Check boot up sequence.
(4)Check control signal: a.) Check CPU control signal(ADS#,BRDY#) is ok or not b.) Check PCI control signal(FRAME#,IRDY#,TRDY#) is ok or not c.) Check others control signal is ok or not
00(no data) (1)Change BIOS (2)Check bios voltage (3)Check BIOS CLK (4)Check LAD0~3 (5)Check BIOS control signal (6)Check CPU control signal 00(Have address & data) (1)CPU N/B:HD0~63,HA3~HA31,control signal open or short (2)N/BS/B:PCI BUS(AD0~AD31,CBE0~CBE3) or HUB Link(HL0~HL10) or V_link or LDT BUS open or short (3)S/BBIOS:ISA BIOS(SA0~SA19,SD0~SD7) or LPC BUS (LAD0~LAD3) open or short
POST C0, D0
C0 (Award) D0 (AMI) (1)Change BIOS (2)Check HD0~63 signal open or short (3)Check HA3~31 signal open or short (4)Check AD0~31 signal open or short (5)Check SM BUS is ok or not (6)Check all Voltage is ok or not ,especially 2.5V,3VS (7)Check all CLK is ok or not (9)Check SB, especially for Intel ICH4
05 (Award) (1)Check KBC CLK is ok or not (2)Check KBC voltage is ok or not (3)Check KBC address,data,control signal is open or short (4)Change KBC
POST 31,3D,41
31,3D (Award) (1)Check KBC CLK is ok or not (2)Check K/B problem (3)Check CPU control signal(HITM#,ITIN,ITNK#)is open or short (4)Check N/B control signal is open or short 41 (Award) (1)Change BIOS (2)Check SA0~SA16 is Open or short (3)Check MEMR#,MEMW# is open or short (4)Check HA3~31 is open or short
1 long
1long, 2 short Repeating (endless loop) 1long, 3short High frequency beeeps while running
Video adapter error Memory error No video card or bad video RAM
Overheated CPU
Repeating High/Low
CPU
The CMOS configuration has failed. Restore the configuration or replace the battery if possible
4-3-1
4-3-3 4-3-4 4-4-1 4-4-2 4-4-3
Overview
Diagram Slot Circuit (G1S) New Card Power Circuit Repair Flow Chart Q & A (Repair Experience)
Diagram
+1.5VS +3VS +3VSUS
+3VSUS_PE Power Controller (R5538V001) +1.5VS_PE +3VS_PE
VSUS_ON SUSB_EC
PCIE_TXN3_C PCIE_TXP3_C
SB
PCIE_RXN3_NEWCARD PCIE_RXP3_NEWCARD
CLK_PCIE_NEWCARD
Clock Gen
CLK_PCIE_NEWCARD#
CLK is OK
OK
Measure Voltage is OK ?
Check +1.5VS_PE & +3VS_PE & +3VSUS_PE is OK Check +1.5VS,+3VS,+3VSUS is OK Check VSUS_ON,SUSB_ECis OK
OK
OK
Finish
Chapter 23 EC
EC KB3310 Role
Power sequence control with FCH Keyboard Controller/Touchpad Fan control LCD Backlight control SMBUS
Smart battery Temperature monitor ACPI (PC power management): Sleep/hibernate/wake up/Lid switch SCI System Control Interrupt to FCH
Embedded Controller
GPIO: Control System Power, LED, AC/DC detect, Charge/discharge control SPI BIOS ROM, Firmware (8051) Watch Dog Timer