Missing re-indexing in VHDL fromSLV conversion

[christiaanb]

The generated VHDL for the following

module Test where

import Clash.Prelude
import Clash.Explicit.Testbench

topEntity :: Maybe (Index 16, Unsigned 4) -> Index 16
topEntity (Just (a,_)) = a
{-# NOINLINE topEntity #-}

testBench :: Signal System Bool
testBench = done
  where
    testInput      = stimuliGenerator clk rst (Just (2,0):>Nil)
    expectedOutput = outputVerifier' clk rst (2:>Nil)
    done           = expectedOutput (fmap topEntity testInput)
    clk            = tbSystemClockGen (not <$> done)
    rst            = systemResetGen

fails during during simulation (in modelsim) with:

# ** Error: (vsim-3710) Qualified expression type mark work.test_types.index_16 constraint (3 downto 0) is not same as operand constraint (7 downto 4).
#    Time: 0 ps  Iteration: 3  Instance: /testbench/topentity_ctesttestbench_app_arg