[M68k] Add floating point support

[mshockwave]

Add supports for floating pointer registers, basic instructions and inline assembly.

Foundation

• Subtarget feature. 68k doesn't have builtin floating point support until 68040. Before that, 68020 and '030 use M68881 and M68882 coprocessor for FP computations, respectively. Thus we need a subtarget feature for this. ([M68k] Add basic floating point infrastructures #61802)
• Register file definitions. Data registers (FP0 - FP7), FPCR, FPSR, and FPIAR. ([M68k] Add basic floating point infrastructures #61802)

Basic instruction definitions

Instruction definitions and MC supports for common FP instructions, for instance:

• FMOVE ([M68k] Add basic floating point infrastructures #61802)
• FADD, FSUB, FMUL, FDIV, FABS ([M68k] Add definitions for floating point arithmetic instructions #61803)
• FTST, FCMP, FBcc, FScc ([M68k] Add definitions for basic floating point compare and control flow instructions #61804)

Advanced instruction supports

• Inline assembly supports. ([M68k] Inline assembly support for floating point constructions #61806)
• Codegen supports for the aforementioned instructions. ([M68k] Add codegen support for basic floating point instructions #61805)

[llvmbot]

@llvm/issue-subscribers-backend-m68k

[0x59616e]

Hello @mshockwave ,

May I inquire if we have any plans or milestones established? Additionally, is there a corresponding to-do list for said milestones?

[mshockwave]

Hello @mshockwave ,

May I inquire if we have any plans or milestones established? Additionally, is there a corresponding to-do list for said milestones?

Yeah I will put more detailed milestones for this. In the short term, we have to pass llvm-test-suite, which relies on inline assembly with floating point constructions. For instance:

__asm__ volatile ("fmove%.l %0, %!" : : "dm" (cw))

So for that, we at least need floating pointer register definitions and MC supports for commonly-used floating point instructions.

[mshockwave]

UPDATE: just updated the description to add (preliminary) roadmap for this task.

[0x59616e]

It appears that this is a large-scale project. I'm wondering if it's possible to divide these tasks and list them in a table format ? This could help us keep track of which items are currently under development and avoid any potential duplication of effort.

Something like this:

item	picker
register support	aaa
instruction mc support	bbb
inline support	ccc

[mshockwave]

It appears that this is a large-scale project. I'm wondering if it's possible to divide these tasks and list them in a table format ? This could help us keep track of which items are currently under development and avoid any potential duplication of effort.

Something like this:

item picker
register support aaa
instruction mc support bbb
inline support ccc

Yes I agree. I've created issues for these tasks. Please put yourself as assignee if you want to work on that.

[0x59616e]

Thanks ! Looks like we have so much fun to do.

[glaubitz]

Any news on the M68k backend?