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✨ [cpu] add experimental support for RISC-V Zibi ISA extension #1418

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Merged
merged 11 commits into from
Nov 2, 2025
Merged

✨ [cpu] add experimental support for RISC-V Zibi ISA extension #1418

merged 11 commits into from
Nov 2, 2025

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@stnolting stnolting commented Nov 1, 2025 •
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Add experimental support for the RISC-V Zibi ISA extension (branch with immediate).

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This RISC-V extension has not been ratifified yet! However, LLVM already provides experimental support.

@stnolting stnolting self-assigned this Nov 1, 2025
@stnolting stnolting added enhancement New feature or request risc-v compliance Modification to comply with official RISC-V specs. HW Hardware-related labels Nov 1, 2025
@stnolting stnolting marked this pull request as ready for review November 1, 2025 18:08
@stnolting stnolting changed the title ✨ [cpu] add support for RISC-V Zibi ISA extension ✨ [cpu] add experimental support for RISC-V Zibi ISA extension Nov 1, 2025
@stnolting stnolting merged commit b8d0165 into main Nov 2, 2025
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@stnolting stnolting deleted the zibi_isa_ext branch November 2, 2025 06:19
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enhancement New feature or request HW Hardware-related risc-v compliance Modification to comply with official RISC-V specs.

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