| Safe Haskell | None |
|---|---|
| Language | Haskell2010 |
HsVerilog
Documentation
module HsVerilog.Type
module HsVerilog.Verilog
module HsVerilog.Simulation
module HsVerilog.Library
hsverilog-0.1.0: Synthesizable Verilog DSL supporting for multiple clock and reset
| Safe Haskell | None |
|---|---|
| Language | Haskell2010 |
HsVerilog
module HsVerilog.Type
module HsVerilog.Verilog
module HsVerilog.Simulation
module HsVerilog.Library