kunal ghosh (vlsisystemdesign.com)

This webinar was conducted on 31st March 2018 with Rohit, CEO Paripath Inc.

We start with Electronic design automation and what is machine learning. Then we will give overall introduction to categories of machine learning (supervised and unsupervised learning) and go about discussing that a little bit. Then we talk about the frameworks which are available today, like general purpose, big data processing and deep-learning, and which one is suitable for design automation. This is Machine… Show more

This webinar was conducted on 31st March 2018 with Rohit, CEO Paripath Inc.

We start with Electronic design automation and what is machine learning. Then we will give overall introduction to categories of machine learning (supervised and unsupervised learning) and go about discussing that a little bit. Then we talk about the frameworks which are available today, like general purpose, big data processing and deep-learning, and which one is suitable for design automation. This is Machine Learning in general with a focus on CAD, EDA and VLSI flows.

Then we talk about Applied Theory (data sets, data analysis like data augmentation, exploratory data analysis, normalization, randomization), as to what are the terms and terminologies and what do we do with that, accuracy, how do we develop the algorithm, essentially the things that are required to develop the solution flow, lets say, you as the company wants to add a feature in your product using machine learning, what you would be doing, and what your flow will look like and this is what is shown as pre-cursor of flight theory as what you should be looking out.

And then we start with regression, which is first in supervised learning. In the regression, we will give couple of example, like first is resistance estimation, second is polynomial regression which is capacitance estimation. For resistance estimation, we have the dataset from 20nm technology. And finally, we go on to create a linear classifier using logistic regression.

About Rohit - Rohit Sharma is Founder and CEO of Paripath Inc based in Milpitas, CA. He graduated from IIT Delhi. He has authored 2 books and published several papers in international conferences and journals. He is passionate about many technical topics including Machine Learning, Analysis, Characterization and Modeling, which led him to architect guna - an advanced characterization software for modern nodes.He currently works for Paripath Inc. Show less

Do you want to build just verilog models or high-quality verilog models in half the time?

Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your… Show more

Do you want to build just verilog models or high-quality verilog models in half the time?

Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser?

How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”. I encourage and welcome you to think in the right direction with experts from this field in my webinar on “Pipelining RISC-V with Transaction-Level Verilog” which was conducted on 10th Feb’ 2018 with Steve Hoover, Founder of Redwood EDA and Makerchip Platform

This webinar is really important for people who have taken up my RISC-V ISA course on Udemy, as we will show efficient RTL implementation of some instructions in this one.

Enjoy the webinar and Happy Learning.... Show less

First, let’s define better? Better in terms of Power. Performance and Area

Every VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis – practically everyone is doing timing ECO at every step of their flow. I, being a part of Signoff timing analysis and Physical Design world, am doing ECO almost every day, and so I understood that its more than adding buffer and up-sizing/downsizing cells.

All of the… Show more

First, let’s define better? Better in terms of Power. Performance and Area

Every VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis – practically everyone is doing timing ECO at every step of their flow. I, being a part of Signoff timing analysis and Physical Design world, am doing ECO almost every day, and so I understood that its more than adding buffer and up-sizing/downsizing cells.

All of the factors or ways shown in above image impacts either dynamic power or short-circuit power or leakage power. The question is, do you know why do we still do it? Do you know how can we still do with minimally impact on other parameters? Yes, No, Don’t Know….

It’s time to unveil more than 9 strategies to do timing ECO and below are few of them

Routing congestion aware timing ECO
Path based analysis ECO for selected endpoints
Replicated modules based timing ECO
Legalized timing ECO
Margin based timing ECO

…..and many more…

See, I told you, timing ECO is more than just adding buffers and sizing cells…Do you want to know all the strategies?
Do you want to be a better timing engineer? Engineering includes tons of changes and modifications from inception to final product. Hence its called Engineering Change Order (ECO)

Welcome all of you to my "Timing ECO webinar", which was conducted along with ~50people on 6th Jan, 2018. Join and re-live the webinar. Show less

This course is in continuation with my previous course "VSD - RISCV : Instruction Set Architecture (ISA) - Part 1a" which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture.

All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course atleast 70%. This course deals with some advanced topics of multiply… Show more

This course is in continuation with my previous course "VSD - RISCV : Instruction Set Architecture (ISA) - Part 1a" which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture.

All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course atleast 70%. This course deals with some advanced topics of multiply extension (RV64M) and floating point extension (RV64FD) of the RISC-V architecture - An important one needed in today's fast changing computing world.

We also have explored some facts about hardware, which is the basis of next course (to be launched soon) where we will code the RISC-V ISA using verilog.

So let's get started - again....Happy Learning

Acknowledgements -

I would like to Thank SiFive, a company that was founded by the creators of RISC-V ISA.

I would also like to Thank Prof. David Patterson and his book "Computer Organization And Design - RISCV edition" which immensely helped in the making of this course.

Let's get inside computers... Show less

In static timing analysis - part 1 course, we introduced you to basic and essential timing checks, like cppr, gba, pba, etc. In this course, we are focusing on application of these concepts on real chip using opensource sta tool called 'Opentimer'. There is an amount of homework needed to make this tool work, but you know what, looking and feeling the power of this opensource tool, you will find the effort is worth taking

Why its worth? Because, you can now analyze your chip at $0 right… Show more

In static timing analysis - part 1 course, we introduced you to basic and essential timing checks, like cppr, gba, pba, etc. In this course, we are focusing on application of these concepts on real chip using opensource sta tool called 'Opentimer'. There is an amount of homework needed to make this tool work, but you know what, looking and feeling the power of this opensource tool, you will find the effort is worth taking

Why its worth? Because, you can now analyze your chip at $0 right from your home. Isn't that FREEdom that we have been looking for? In my advanced courses, including this one, the prime focus is on how to analyze complex chips like USB controller or DDR using Opentimer.

Opentimer has been developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA. It supports important features like PBA, CPPR, block based analysis, and many more.

I am using this tool in this course for explaining the concepts from STA-part 1 and also for some interface analysis that we will be looking in this course.

So, hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !! Show less

Physical designers and CMOS fabrication team communicates with each other, and this course says it 'How?'

While physical designers use all the outputs from experiments performed by fabrication department, this course will demonstrate the best of both worlds and connect them through exchange of certain files in certain format

This way, custom layout designers get to know an insight how does fabrication works, fabrication engineers get to know, how layout engineers uses their… Show more

Physical designers and CMOS fabrication team communicates with each other, and this course says it 'How?'

While physical designers use all the outputs from experiments performed by fabrication department, this course will demonstrate the best of both worlds and connect them through exchange of certain files in certain format

This way, custom layout designers get to know an insight how does fabrication works, fabrication engineers get to know, how layout engineers uses their information. So this course is a place where both meet, talk and connect.

Also, the standard files needed to draw and simulate layout, are being taken, deduced and created from scratch and on the fly. This is, by far, the best way to understand layout, and I can promise you an exciting journey throughout this course

Course is structured to explain the CMOS packaging and fabrication steps in beginning, followed by software and files used to draw and simulate layout, and look into DRC rules.

Next, we will take a simple CMOS inverter and apply all concepts learned above. Finally, we will learn the 'Art of layout' using Euler's path. This is where you will solve complex functions and draw a layout out of it.

Welcome you all to my course and Happy Learning!!

See you in class! Show less

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks.

This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of… Show more

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks.

This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!
Show less

So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis.

OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk,

But, sit back, and give it a thought "Have you done it all?"​ "Did you know, where does the delay of a cell actually comes from?"​ "We have learnt about delay models, but are the models accurate?"​ "How do you verify, if what you are doing in static timing… Show more

So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis.

OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk,

But, sit back, and give it a thought "Have you done it all?"​ "Did you know, where does the delay of a cell actually comes from?"​ "We have learnt about delay models, but are the models accurate?"​ "How do you verify, if what you are doing in static timing analysis, is correct?"​ and many more.

These are some of curious questions we wonder about, but hardly find any answers. Even if we found the answers, as a passionate learner, we are still more curious to do some practical things on our own.

And, here's the answer to all of them. SPICE (Simulation Program for Integrated Circuit Emphasis). This course has answers to almost all questions that you might have as a serious timing analyst

So let's get started and keep those questions coming in the forum, and I will answer all of them.

See you in class !! Show less

This is a follow-up course on my previous one "Circuit design and SPICE simulations - Part1"

It is a must, that you go through Part 1 of this course, to fully understand and apply using open source tools. This course will help you do some advanced quick SPICE simulations, while you analyze the behavior of your devices.

In this course we will cover:

1.Voltage Transfer Characteristics - SPICE simulations

2.Static behavior Evaluation : CMOS inverter… Show more

This is a follow-up course on my previous one "Circuit design and SPICE simulations - Part1"

It is a must, that you go through Part 1 of this course, to fully understand and apply using open source tools. This course will help you do some advanced quick SPICE simulations, while you analyze the behavior of your devices.

In this course we will cover:

1.Voltage Transfer Characteristics - SPICE simulations

2.Static behavior Evaluation : CMOS inverter Robustness

•Switching Threshold

•Noise margin

•Power supply variation

•Device variation

So let's get started (again) and keep those questions coming in the forum, and I will answer all of them.

See you in class !! Show less

The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.

We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design. And also shared our… Show more

The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.

We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design. And also shared our industrial experience to give the technological exposure of current development in chip world... Show less

Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.

Crosstalk is the interference caused due to communication between the circuits

Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.

Clock Tree Networks are Pillars and Columns of a Chip.

With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.

The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.

This course is a follow-up course of "VLSI Academy - Clock tree synthesis - Part 1". So its highly recommended to go through Part 1 of clock tree synthesis

Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop.

While we plan to add some experimental videos and courses very soon, as a supplement, this one has real time examples and problems that you see on a real chip, and even… Show more

This course is a follow-up course of "VLSI Academy - Clock tree synthesis - Part 1". So its highly recommended to go through Part 1 of clock tree synthesis

Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop.

While we plan to add some experimental videos and courses very soon, as a supplement, this one has real time examples and problems that you see on a real chip, and even solutions to those problems

The course is structured in below format:

1) Introduction

2) Clock tree optimization checklist

3) How to build clock tree for uneven spread of clock end-points

4) Power aware clock tree synthesis

5) Static timing analysis with real clocks

Sounds interesting !! Right !! So get in and have the greatest learning experience like you had never before

See you in class!!
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This course is about Basic concepts of VLSI System Design. The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.The introductory video series focuses on the basic elemental physics and electrical characteristics of MOS Transistor.

Building a chip is like building a city...

This was the mantra with which we started our company in 2011. Now that we have covered major components of chip designing through our online courses, I think this is the right time to move from "chip designing" to "chip planning"

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters… Show more

Building a chip is like building a city...

This was the mantra with which we started our company in 2011. Now that we have covered major components of chip designing through our online courses, I think this is the right time to move from "chip designing" to "chip planning"

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.

Do you want to know what it is like to build a city? Did you know there is no standard definition for GPIOs? Thats the whole point of designing an SOC. Figuring out what things you are going to control outside of the CPU and memory mapping them.

If you look at any microcontroller e.g. PIC microcontroller, the only way to know how you access their ADC or their UART is to go look at their documentation and find out wheres the memory map address for this

Do you want to know how to build and configure your own System-on-Chip (SoC)? Do you want to write your own data sheet?

I welcome you to my webinar which was conducted on Mar 10, 2018. Enroll with myself, Tim Edwards and Mohamed Kassem, and rise above, by being a Core SoC designer and build your own datasheet.

This is the perfect webinar for to grow and stay ahead of curve in Semiconductor and Chip design. Stay tuned and happy learning....

All the best, and I will see you in webinar.. Show less

Be it in any field - Change is inevitable. Let’s change the way we used to do Physical design. This time, no need to install tools on laptop, no licenses needed, no hidden costs, just your gmail login id and you are ready to design your first chip online. Find it hard to believe?

I welcome you to my first “Physical Design” Webinar that happened on 20th Jan 2018 at 9am IST. This is 3-hour action-packed webinar with myself being the host and below 3 people from industry

Rajeev… Show more

Be it in any field - Change is inevitable. Let’s change the way we used to do Physical design. This time, no need to install tools on laptop, no licenses needed, no hidden costs, just your gmail login id and you are ready to design your first chip online. Find it hard to believe?

I welcome you to my first “Physical Design” Webinar that happened on 20th Jan 2018 at 9am IST. This is 3-hour action-packed webinar with myself being the host and below 3 people from industry

Rajeev Srivastava -

Rajeev is technical advisor to webchip and also was one of the developers of Proton while at Silverline Inc. Currently he is a Sr Principal Physical Design Engineer at NXP. While at Silverline, he was a expert user of Proton and has worked with customers to use proton successfully on many chip design projects. He will be helping with the webinar today and show how to run the tools and also answer proton related questions.

Aditya Pratap -

Aditya is the main developer and chief architect of Webchip.He was also one of the main developers of open source EDA tool proton that we will see in action today in our webinar.

Sanjeev Gupta -

Sanjeev is an VLSI & System design expert and also chief of operations at webchip.

Finally one word - 'LIVE' - pin placement, verification and routing on WEB. All with zero license fee using industry grade EDA tool. That's innovation. This is something which has never happened before.

Learn from the best, and expect a shift in your professional thinking.

I will see you all in webinar and happy learning Show less

RISC-V is a free and open RISC instruction set architecture. and was originally developed in Computer Science division of the EECS Department at the University of California, Berkeley

This course will talk a lot about RISC-V ISA from scratch, also including a section about why do we even need a computer architecture and how real-time day-to-day apps run on a computer, with examples

The final aim of this course is to help everyone to build a robust specifications, which is the… Show more

RISC-V is a free and open RISC instruction set architecture. and was originally developed in Computer Science division of the EECS Department at the University of California, Berkeley

This course will talk a lot about RISC-V ISA from scratch, also including a section about why do we even need a computer architecture and how real-time day-to-day apps run on a computer, with examples

The final aim of this course is to help everyone to build a robust specifications, which is the very first criteria behind system design. In the upcoming courses,, these specifications will be coded in RTL hardware description language using verilog/vhdl and finally the RTL will placed and routed using opensource EDA tool chain.

This course will walk you through the specifications, starting from signed/unsigned integer representation till RV64IMFD Instruction set with some really cool images and examples. The conventions like "IMFD" will also be explored in a unique fashion, which is being never done before and any micro-processor or micro-controller related courses

Acknoledgements -

I would like to Thank SiFive, a company that was founded by the creators of RISC-V ISA.

I would also like to Thank Prof. David Patterson and his book "Computer Organization And Design - RISCV edition" which immensely helped in the making of this course.

Let's get inside computers... Show less

As promised, again, TCL Programming - Part 2 course has been pre-launched with 5 videos. Many more to come, as always.

This course is a unique mixture of TCL programming being used in manipulating output EDA tools, creating EDA commands (like call_timer, read_sdc, and many more) and generating output timing summary report. The concept of this course can be extended to create any command, moreover, create any kind of UI you wish to.

Certain per-requisites are necessary for this… Show more

As promised, again, TCL Programming - Part 2 course has been pre-launched with 5 videos. Many more to come, as always.

This course is a unique mixture of TCL programming being used in manipulating output EDA tools, creating EDA commands (like call_timer, read_sdc, and many more) and generating output timing summary report. The concept of this course can be extended to create any command, moreover, create any kind of UI you wish to.

Certain per-requisites are necessary for this course i.e. you need to complete TCL programming - Part 1 course, atleast 50% to enjoy this course to the fullest. As with my other courses, I am very sure, this course will also be one of "Best-Sellers".

I can guarantee you, this time, your ride with this course will be more memorable one, as its a "first-of-its-kind" "state-of-the-art" unique blending of TCL with EDA. So ride along, and enjoy while learning. More videos are on its way, stay tuned.... Show less

The Expert In Anything Was Once A Beginner ----
And I really believe in that...

I was a novice in TCL programming 10 years back. One thing that led from novice to an expert is "Practice"

Be it learning scripting language or an EDA tool, nothing beats 'concepts'. I have been proving this in my courses, how learning a tool is the last 5% task of entire learning flow.

My students, who have been working with on several projects and also learning through my courses, have not… Show more

The Expert In Anything Was Once A Beginner ----
And I really believe in that...

I was a novice in TCL programming 10 years back. One thing that led from novice to an expert is "Practice"

Be it learning scripting language or an EDA tool, nothing beats 'concepts'. I have been proving this in my courses, how learning a tool is the last 5% task of entire learning flow.

My students, who have been working with on several projects and also learning through my courses, have not only learned semiconductors, but lived the journey. And I promise, the same will happen with my this course on TCL scripting as well.

I have been using the same approach in last 10 years for solving problems, be it a TCL script issue or an issue with STA timing violation or an issue with DRC or an issue with floor planning or an issue with routing congestion, you name it..

You will witness the same in all my courses and in this one as well. Let's unveil the concepts of data flow and manipulation using TCL scripts Show less

***pre-launched with 9 videos...please ask for discount coupon***

If you are STA engineer or PNR engineer or CTS engineer or, in general, a physical designer or Synthesis engineer, you must have definitely come across the word 'Library'. This course explains you, in detail, what it exactly means.

You can call Library as the soul and heart of Semiconductor industries. Without them, you can't have single chip out. Without the knowledge of Libraries, all other courses are… Show more

***pre-launched with 9 videos...please ask for discount coupon***

If you are STA engineer or PNR engineer or CTS engineer or, in general, a physical designer or Synthesis engineer, you must have definitely come across the word 'Library'. This course explains you, in detail, what it exactly means.

You can call Library as the soul and heart of Semiconductor industries. Without them, you can't have single chip out. Without the knowledge of Libraries, all other courses are incomplete.

Guess what, you are at the right page. This course gives a comprehensive overview of characterization techniques and advanced modelling of circuits for modern and advanced nodes.

Not only that, you will see what goes behind designing a simple single input inverter. The gates like inverter, buffer, AND, OR are all called as cell, and you will be amazed to see how are the represented in real IC design.

This course is designed in collaboration with leading characterization company Paripath, who have designed the state-of-the-art characterization software called GUNA

I would like to Thank complete Paripath team for helping me in designing experiments for this course. This course is motivated by desire to fill gap on characterization and modelling

Get in right now and have an unforgettable journey of your life...

Happy Learning!! Show less