Puneet Mittal

Language/Tools: TCL, Shell Scripts, ICC, Design Compiler, StarRCXT, Hercules/ICV/Primeyield,
Description : In order to deliver quality product to our customer a proper validation/Regression testing/QA is required before any release.
Role :
Managing:
 Managing the complete QA activity (Quality analysis) of every release in the team. Complete responsible to deliver quality product outside the Lynx Design system team.
 Developing the test plan for the validation process of… Show more

Language/Tools: TCL, Shell Scripts, ICC, Design Compiler, StarRCXT, Hercules/ICV/Primeyield,
Description : In order to deliver quality product to our customer a proper validation/Regression testing/QA is required before any release.
Role :
Managing:
 Managing the complete QA activity (Quality analysis) of every release in the team. Complete responsible to deliver quality product outside the Lynx Design system team.
 Developing the test plan for the validation process of Lynx-FRS and Lynx- Production Flow and assigning that to different team members.
 Monitoring the progress of Validation and if require arrange extra resources to finish it before time.
 Taking decision to fix any issue/bug found during QA process in the current release or keeping that in the know issue section of Release document.
Technical:
 Responsible for regression testing on several in house designs of Technology data generated through FRS.
 Responsible to find out the bug, find out the root cause of that bug, propose the solution and if possible then fixing that issue.
 Responsible to figure out whether a particular Bug is because of Foundry Data/ Lynx FRS system / Lynx Production Flow. Show less

Language/Tools : Hercules, ICV, PrimeYield-LCC, Primeyield-CAA, ICC (IC compiler), Milkyway
Description : Directly working with Layout designers and CAD groups in India that use Synopsys' Physical Implementation, Verification tool.
Role :
Technical:
 Responsible to clean the Design and Reference Flow for different technology/node and Foundry with respect to Dummy Metal (DM)/Dummy Oxide (DOD) fill, DRC/LVS, Antenna/EM, DFM (CAA/LCC/CMP) or any other Physical verification related… Show more

Language/Tools : Hercules, ICV, PrimeYield-LCC, Primeyield-CAA, ICC (IC compiler), Milkyway
Description : Directly working with Layout designers and CAD groups in India that use Synopsys' Physical Implementation, Verification tool.
Role :
Technical:
 Responsible to clean the Design and Reference Flow for different technology/node and Foundry with respect to Dummy Metal (DM)/Dummy Oxide (DOD) fill, DRC/LVS, Antenna/EM, DFM (CAA/LCC/CMP) or any other Physical verification related issues.
 Responsible for QOR (Quality Of Result) of DRC/LVS checks across different Tools (Hercules/ICC/ICV) throughout the design.
 Communicating with foundry for rule Deck modification/enhancements.
Major accomplishment :
 Cleaned the TSMC40LP/TSMC40GP/CHARTED65LP/SMIC90LL tech data with respect to DRC/LVS/DFM/DFY issues.
 Getting expertise in Hercules, ICV, PrimeYield-LCC and PrimeYield-CAA tools.
 Giving training to other Team members related to Chip Finishing concepts and tools.
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Details:
The LSI design flow uses an internal leakage power recovery utility run from within PrimeTime. This utility was discussed previously at Boston SNUG 2008 [1] by Bruce Zahn and has been used in the LSI design flow on many production designs. The technique of leakage power recovery run in the signoff environment has achieved significant leakage reduction.
LIPO is efficient to carry out the leakage swap without bringing timing violations. After implement the scripts, the leakage… Show more

Details:
The LSI design flow uses an internal leakage power recovery utility run from within PrimeTime. This utility was discussed previously at Boston SNUG 2008 [1] by Bruce Zahn and has been used in the LSI design flow on many production designs. The technique of leakage power recovery run in the signoff environment has achieved significant leakage reduction.
LIPO is efficient to carry out the leakage swap without bringing timing violations. After implement the scripts, the leakage power get obviously decreasing.

Tools: Primetime(PT, PTSI) , LIPO, TCL

Role:
# Understanding the LIPO Tool.
# Adding the Testcases in the PT Regression Suite to own Testing/Validation side (In terms of Primetime Version and Feature changes).
# Support of LIPO Tool across Design team.

Achievements:
# Understood the Power Recovery + Optimization concept and Insight knowledge of LVT/HVT/RVT cells.
# Understood the DMSA concepts.
# Successfully Integrate the Testcase for Testing/Validation.
# Handled This Project Independently from Planing to Execution. Show less

Language/Tools: Primetime(PT, PTSI), StarRcxt ,Milkyway, ICC, TCL, Shell
Role:
Technical:
1) Learning the Hyperscale Flow with the Help of Synopsys ACs and my US counterpart.
2) Develop the Hyperscale Flow as per Design Requirement and Help India Design Team to adopt HS (HyperScale) in their LIVE design.
3) Worked Over Constraint Extractor (Timing Block's Constraints generation tool from the Full Flat Constraint), which help design team to reduce the TAT in their Design.
4)… Show more

Language/Tools: Primetime(PT, PTSI), StarRcxt ,Milkyway, ICC, TCL, Shell
Role:
Technical:
1) Learning the Hyperscale Flow with the Help of Synopsys ACs and my US counterpart.
2) Develop the Hyperscale Flow as per Design Requirement and Help India Design Team to adopt HS (HyperScale) in their LIVE design.
3) Worked Over Constraint Extractor (Timing Block's Constraints generation tool from the Full Flat Constraint), which help design team to reduce the TAT in their Design.
4) Generate different Data (Accuracy + RunTime + Memory +QOR ) with and without HS and presented report about the Improvement internally and in SNUG-PT-SIG. Show less

Description:
LSI have internal standards for SignOff Tool qualification before deploy within Design Team. Only Qualified version of Tool can be used by Design Team. Our team was responsible to qualify and deploy Signoff Tools (StarRcxt and PrimeTime) with proper methodology + guidance across design teams. We were also responsible for all kind of Support during design Cycle (Related to PT, StarRcxt)

Role:
Qualify:
# Complete the Qualification (Functional, Accuracy… Show more

Description:
LSI have internal standards for SignOff Tool qualification before deploy within Design Team. Only Qualified version of Tool can be used by Design Team. Our team was responsible to qualify and deploy Signoff Tools (StarRcxt and PrimeTime) with proper methodology + guidance across design teams. We were also responsible for all kind of Support during design Cycle (Related to PT, StarRcxt)

Role:
Qualify:
# Complete the Qualification (Functional, Accuracy ,Version-to-version, Runtime/Memory verification) of StarRcxt and Primetime as per the LSI standards.
# Beta-testing + New Feature testing in StarRcxt and Primetime.
# Make proper Changes in Design Flow or Methodology as per Requirement to support New feature/Version of SignOff Tool.
Support:
# Support the deployed Version of StarRcxt and Primetime along with LSI specific Methodology.
# Interaction with Design Team for their issues (During the design cycle) and figure out whether issues are in Design Inputs / Methodology or Design Flow / EDA tools.
# Provide Ontime workaround Or Fixes (Of Issues) after Interacting with Synopsys AC/ R&D team or By changing/modifying Methodology or Design flows

Accomplishment:
# Learned - How to interact/communicate Different teams/vendors/people professionally.
# Experienced + Learned- Real time challenges in design at different stages.
# Deployed 3 versions of StarRcxt (for 28nm, 40nm) and 5 versions of Primetime.
# Supported 2 Designs ( Show less

Language/Tools: TCL, GMAKE, STAR-RCXT, Design compiler (DC), Milkyway, Primeyield-LCC
Description : In order to avoid any surprises during the design because of incorrect input data or incompatibility of hard-ip, with the help of FRS, designer can clean up the library data and successfully integrate these libraries & IP into Synopsys Galaxy implementation flow. FRS takes the raw data from foundry (TSMC/CP/GF/SMIC etc) of different technology nodes (65nm, 40nm, 45nm, 90nm etc), it does… Show more

Language/Tools: TCL, GMAKE, STAR-RCXT, Design compiler (DC), Milkyway, Primeyield-LCC
Description : In order to avoid any surprises during the design because of incorrect input data or incompatibility of hard-ip, with the help of FRS, designer can clean up the library data and successfully integrate these libraries & IP into Synopsys Galaxy implementation flow. FRS takes the raw data from foundry (TSMC/CP/GF/SMIC etc) of different technology nodes (65nm, 40nm, 45nm, 90nm etc), it does data processing and it rearranges it in a structure which is suitable for Lynx design system.
Role :
Managing:
 Second owner of FRS.
 Responsible for taking correct and proper decisions during projects planning and execution.
 Monitoring the progress of different tasks and providing the appropriate feedback.
 Propose the new and innovative ideas for the improvement of functionality/quality of FRS.
Technical:
 Analyzing the data and come across with the conclusion about the type of changes and where it is require.
 Implementing various TCL based scripts/wrappers for FRS development.
 Coordinate with the team member to solve any issues during the development of FRS.
 Working over different foundry (TSMC, CP, SMIC, IBM, CHARTED, UMC) and technical node (90nm, 65LP, 65GP, 40LP,40GP).
 Working with ARM and TSMC stdcell library.
Major accomplishment :
 Playing a Key role in development of Roadmap of FRS.
 Delivered successfully Alpha, 3 Beta, LCA, GA, 3major and 9 service pack releases.
 Coordinating with different foundries (TSMC, CP, SMIC, CHARTED, UMC) for resolving any data correctness/compatibility issue. Show less

Language/Tools: TCL, GMAKE, ICC (IC compiler), Milkyway, Hercules, ICV, PrimeYield,
Description : Lynx Production Flow is a hierarchical RTL2GDS production flow based on Synopsys Reference Methodologies. It is kept up-to-date with latest Synopsys tool versions & Synopsys tool recommended RM’s. Lynx automates flow configuration and execution to improve the productivity of the design team.
Role :
Managing:
 Working as a Primary owner of Production flow of TSMC40GP and CP32LP.
… Show more

Language/Tools: TCL, GMAKE, ICC (IC compiler), Milkyway, Hercules, ICV, PrimeYield,
Description : Lynx Production Flow is a hierarchical RTL2GDS production flow based on Synopsys Reference Methodologies. It is kept up-to-date with latest Synopsys tool versions & Synopsys tool recommended RM’s. Lynx automates flow configuration and execution to improve the productivity of the design team.
Role :
Managing:
 Working as a Primary owner of Production flow of TSMC40GP and CP32LP.
 Working as a Secondary owner of Production flow of TSMC40LP and Charted65LP.
 Communicating with the foundry/vendor for any updates in the Tech/Stdcell data.
Technical:
 Responsible of updating the flow as per the Synopsys’s Tool version.
 Responsible of updating the flow as per any change/modification in the foundry tech/stdcell data.
 Responsible of fixing any bugs/issues finding during the validation/QA process.
 Updating the flow as per the specific requirement raised by the customer.
Major accomplishment :
 Developed a production Flow of CP32LP using ARM library
 Developed a production flow of TSMC40GP using ARM library.
 Helped to develop the production Flow for TSMC40LP. Show less

Language/Tools: Hercules, ICV, ICC (IC compiler), Milkyway, TCL, Zroute, Lynx Design System.
Description : Released the reference flow which is pre-validated for the Common Platform 32nm technology.
Role :
Technical:
 Understood the requirement and modified the Foundry provided data.
 Prepare the Full reference flow (with the help of other team member) and validated it on few in-house design.
Managing:
 Working as a Primary owner of CommonPlateform32nm reference… Show more

Language/Tools: Hercules, ICV, ICC (IC compiler), Milkyway, TCL, Zroute, Lynx Design System.
Description : Released the reference flow which is pre-validated for the Common Platform 32nm technology.
Role :
Technical:
 Understood the requirement and modified the Foundry provided data.
 Prepare the Full reference flow (with the help of other team member) and validated it on few in-house design.
Managing:
 Working as a Primary owner of CommonPlateform32nm reference flow development.
 Syncing with different team member to release it on time.
 Leveraging the efforts of other team member for this activity.
Major accomplishment:
 On-time release of CP32LP reference flow (module1) in very short time (5 weeks). Show less

Language/Tools: Mtcl, Perl, Blast fusion, Quartz RC, Quick Cap, LSF, Talus
Description : These rules consist of Capacitance, Resistance, CMP, RHO, OPC, IMD, Density and Trap rules. These are for different technologies (180nm to 45nm) and for different foundries (TSMC, SMIC, UMC, CSM, IBM). This work involves the understanding of Dielectric stack, Metallization stack, Quick cap Extraction Engine, Blast fusion or Quartz RC extraction engine, the flow use to generate the parasitic rules for… Show more

Language/Tools: Mtcl, Perl, Blast fusion, Quartz RC, Quick Cap, LSF, Talus
Description : These rules consist of Capacitance, Resistance, CMP, RHO, OPC, IMD, Density and Trap rules. These are for different technologies (180nm to 45nm) and for different foundries (TSMC, SMIC, UMC, CSM, IBM). This work involves the understanding of Dielectric stack, Metallization stack, Quick cap Extraction Engine, Blast fusion or Quartz RC extraction engine, the flow use to generate the parasitic rules for the Blast Fusion/Talus system and to extract the Detailed Standard Parasitic Format (DSPF) or Standard Parasitic Exchange Format (SPEF) data.
Major contribution:
 Developed the Parasitic rules using Blast Fusion or Quartz RC, a rule based 3D full-chip parasitic extractor, for various experiments like ground, cross-over, cross-under, parallel, m-parallel, variation keeping in consideration the various fabrication effects like optical proximity correction (OPC), chemical mechanical polishing(CMP), trap tangents etc.
 Correlated developed parasitic rules with the industry standard (STAR RCXT extractor)
 Coordinated with the team at customer site for solving their issues related to parasitic rules.
 Performed QA of every release in the team.
 Implemented different scripts to automate the manual work in developing rules.
Clients : TI, Qualcomm, IBM, Intel, Broadcom, Nvidia, LSI, etc. Show less

Language/Tools: Mtcl, Perl, Blast fusion, Talus
Description : These rules consist of Design rules, Layer mapping rules, EM rules, slotting rules and Antenna rules. This work involve the basic understanding of metallization stack, different types of grids, width and spacing dependent rules, VIA rules, mapping of various GDSII layers number, current density in layers, Antenna Issues and the use of jumper or diode to solve them.
Major contribution:
 Developed the routing rules… Show more

Language/Tools: Mtcl, Perl, Blast fusion, Talus
Description : These rules consist of Design rules, Layer mapping rules, EM rules, slotting rules and Antenna rules. This work involve the basic understanding of metallization stack, different types of grids, width and spacing dependent rules, VIA rules, mapping of various GDSII layers number, current density in layers, Antenna Issues and the use of jumper or diode to solve them.
Major contribution:
 Developed the routing rules library for different technologies (180nm, 130nm, 90nm, 65nm, 45nm etc) for the different foundries (TSMC, SMIC, UMC, CSM etc).
 Coordinated with the team at customer site for solving their issues related to routing rules.
 Performed QA of every release in the team.
 Implemented different scripts to automate the manual work in developing rules.
Clients : TI, Qualcomm, IBM, Intel, Broadcom, Nvidia, LSI, etc. Show less

Language/Tools: C, Cadence Skill Language, Perl, Cadence Virtuoso
Major Contribution:
 Developed an Algorithm and an Automation flow from scratch for preparing the Regression cells database to validate DRC Deck for any technology node.
Major Accomplishment :
 Understood thoroughly about Cadence-virtuoso tool, its database structure, Skill architecture and its implementation, inter-process communication, APIs for graphic editor and database access.
 Implemented in real time,… Show more

Language/Tools: C, Cadence Skill Language, Perl, Cadence Virtuoso
Major Contribution:
 Developed an Algorithm and an Automation flow from scratch for preparing the Regression cells database to validate DRC Deck for any technology node.
Major Accomplishment :
 Understood thoroughly about Cadence-virtuoso tool, its database structure, Skill architecture and its implementation, inter-process communication, APIs for graphic editor and database access.
 Implemented in real time, the basics of data structure, pre-defined algorithms and image processing concepts.
 Converted the turnaround time from 6 month (manual work) to 6 weeks. Show less

Tools : Cadence- Virtuoso, Mentor-Graphic IC studio, Caliber-DRC, Caliber-LVS, Eldo,
Description : Project involves designing a 2 stage fully differential Op-Amp circuit with a feedback circuit (Common mode Feedback) satisfying certain specification. It follows the complete flow of Full custom Analog/mixed signal circuit design as- Creating Schematic, Creating Symbol, Schematic Simulation, different iterations to satisfy the given specification, Net-list generation, Creating Layout, DRC… Show more

Tools : Cadence- Virtuoso, Mentor-Graphic IC studio, Caliber-DRC, Caliber-LVS, Eldo,
Description : Project involves designing a 2 stage fully differential Op-Amp circuit with a feedback circuit (Common mode Feedback) satisfying certain specification. It follows the complete flow of Full custom Analog/mixed signal circuit design as- Creating Schematic, Creating Symbol, Schematic Simulation, different iterations to satisfy the given specification, Net-list generation, Creating Layout, DRC, LVS, Parasitic Extraction, Post Layout simulation. This project corresponds to 180um technology. This work involves the understanding of CMOS, Op-Amps and compensation circuit’s basic.
Role:
 Responsibility involves designing a 2 stage fully differential Op-Amp circuit with a feedback circuit (Common mode Feedback) satisfying certain specification.
 Understanding the specification and draw schematic accordingly
 Create layout accordingly and doing all checks (DRC, LVS) and simulation (Pre-layout and Post-layout). Show less

Language/Tools: C, Cadence Skill Language, Cadence Virtuoso, Caliber.
Description : In order to validate the DRC decks (LSI foundry) developed by the R&D, a set of regression database (in the form of geometries) is required. These geometries also help in determining which structure combination is possible for a particular rule mentioned in the DRC rule deck.
Major contribution:
 Designed the regression cells (geometries of Good and Bad cells) for 90nm and 65nm to validate the DRC… Show more

Language/Tools: C, Cadence Skill Language, Cadence Virtuoso, Caliber.
Description : In order to validate the DRC decks (LSI foundry) developed by the R&D, a set of regression database (in the form of geometries) is required. These geometries also help in determining which structure combination is possible for a particular rule mentioned in the DRC rule deck.
Major contribution:
 Designed the regression cells (geometries of Good and Bad cells) for 90nm and 65nm to validate the DRC rules.
 Tested of DRC rule-deck (90nm) and reported to development team whenever any issue found in the DRC rule-deck.
Major Accomplishment :
 Worked on real project which needs the complete understanding of layout designing, designing layers (as Pwell, Nwell, OD, Poly, Metal layers, VIAs etc), design rules and through knowledge of DRC rule deck. Show less