Drafts by abhishek bhattacharjee
For an organization, it is must to focus on customer relationship management to create strong and... more For an organization, it is must to focus on customer relationship management to create strong and effective customer relationships. CRM helps to make customer loyal, to have competitive position in the market, and to focus on potential consumers. In this paper, i have explained how CRM works in the banking industry.
Papers by abhishek bhattacharjee
Synthesis Lectures on Computer Architecture, 2017
This book provides computer engineers, academic researchers, new graduate students, and seasoned ... more This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of-the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system design, and memory allocation. We show how efficient virtual memory implementations hinge on careful hardware and software cooperation, and we discuss new research directions aimed at addressing emerging problems in this space. Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from the burden of physical memory management by the hardware, the operating system, device drivers, and system libraries. However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling to scale up and scale out to today's systems which now increasingly include exotic hardware accelerators (such as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which run increasingly intensive workloads (such as virtualized and/or "big data" applications). As such, many of the fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, or entirely rebuilt in order to ensure that virtual memory remains viable and performant in the years to come.
2011 IEEE 17th International Symposium on High Performance Computer Architecture, 2011
Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research ha... more Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as chip multiprocessors (CMPs) become ubiquitous, TLB design must be re-evaluated. This paper is the first to propose and evaluate shared last-level (SLL) TLBs as an alternative to the commercial norm of private, per-core L2 TLBs. SLL TLBs eliminate 7-79% of system-wide misses for parallel workloads. This is an average of 27% better than conventional private, per-core L2 TLBs, translating to notable runtime gains. SLL TLBs also provide benefits comparable to recently-proposed Inter-Core Cooperative (ICC) TLB prefetchers, but with considerably simpler hardware. Furthermore, unlike these prefetchers, SLL TLBs can aid sequential applications, eliminating 35-95% of the TLB misses for various multiprogrammed combinations of sequential applications. This corresponds to a 21% average increase in TLB miss eliminations compared to private, per-core L2 TLBs. Because of their benefits for parallel and sequential applications, and their readily-implementable hardware, SLL TLBs hold great promise for CMPs.
Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08, 2008
The design process for chip multiprocessors (CMPs) requires extremely long simulation times to ex... more The design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS. Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35× speedup compared to corresponding full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems.
ACM Transactions on Architecture and Code Optimization, 2013
Translation Lookaside Buffers (TLBs) are critical to overall system performance. Much past resear... more Translation Lookaside Buffers (TLBs) are critical to overall system performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as Chip MultiProcessors (CMPs) become ubiquitous, TLB design and performance must be reevaluated. Our article begins by performing a thorough TLB performance evaluation of sequential and parallel benchmarks running on a real-world, modern CMP system using hardware performance counters. This analysis demonstrates the need for further improvement of TLB hit rates for both classes of application, and it also points out that the data TLB has a significantly higher miss rate than the instruction TLB in both cases. In response to the characterization data, we propose and evaluate both Inter-Core Cooperative (ICC) TLB prefetchers and Shared Last-Level (SLL) TLBs as alternatives to the commercial norm of private, per-core L2 TLBs. ICC prefetchers eliminate 19% to 90% of Data TLB (D-TLB) misses across parallel work...
International Journal of Advanced Research, 2020
The major objective behind writing this research paper is to analyze the complete process of disi... more The major objective behind writing this research paper is to analyze the complete process of disinvestment of the Public Sector Enterprises and outline the effect of the same. The effect of disinvestment of PSUs depends upon the development status of a country. For a developing country such as India, health, education and medicine requires utmost attention and selling of the shares in the PSUs aids the government to provide this attention to the designated areas. The research paper also involves a comparative study of both the old policies of disinvestment followed in India as well as the new policies incorporated by the government. The study will basically facilitate the understanding as to whether the government has been able to cover the loopholes which were evident in the old process. The researchers have selected the topic keeping in mind the significant and critical need to discuss and analyse the whole process of disinvestment of PSUs in India with respect to the present conditions, circumstances, economical and legal sphere. A clear idea on the effect of the same was necessary to be traced. The method of research utilised for the purpose of this research paper is the doctrinal method and involves both a qualitative as well as a quantitative
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Drafts by abhishek bhattacharjee
Papers by abhishek bhattacharjee