Chiplets…Optimized Device Integration, SWaP Performance & Time-to-Market

With the current growth of the defense and space systems market accelerating, the high-reliability microelectronics required for these systems are under ever-increasing pressure to consume less size, weight, power, and cost (SWaP-C), as well as to provide increased performance, indefinite product life-cycle sustainability, and supply chain reliability. Challenges in sourcing high-reliability microelectronics include product availability, along with PCN/ECN and obsolescence issues; increased risk with each supplier needed to source the many devices required for the IC; and rising geopolitical tensions with the potential for supply chain disruptions. Packaged IC manufacturing, aside from ASICs, requires multiple devices and interconnects to produce. With many devices to procure, coordinating IC design and manufacture is often fraught with challenges to overcome, including varying leads times as well as PCN/ECN and obsolescence issues. Additionally, multi-supplier procurement for in-house manufacturing requires coordination with multiple sources at various volumes, requiring inspection, testing, and potentially heterogeneous integration. Is there a better solution to minimize supply chain risks, optimize SWaP-C savings and performance, while also accelerating development and production time?

Chiplets, the next generation of System in Package (SiP) microelectronics, enable the most compact and efficient microelectronics solutions to be created through the integration of multiple devices and functions into a single SWaP-C and performance optimized package.

In this webinar, we will explore how Chiplets efficiently address today's market needs, highlight the key points to be considered with a Chiplet solution, and provide insight into the current state of Chiplets, which have not settled on one industry-wide standard for interconnects, communication protocols, and packaging. Experts in BEOL processing, advanced 2.5/3D heterogenous integration, testing, and component packaging will present the latest developments, standards, protocols, and Chiplet design methodology. Attendees will gain deep insight into the considerations and best practices in leveraging the value and performance of Chiplets for high-reliability systems.

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