Axiomise

Yesterday, in the CadenceCONNECT Club Formal in the UK, our CEO Ashish Darbari showcased a groundbreaking technology CoreProve for end-to-end #formalverification sign-off. Designed by Axiomise experts, CoreProve is an advanced abstraction engine that establishes proof convergence for complex end-to-end checks in formal property checking tools ensuring you don’t miss a bug and prove bug absence. Initial testing on a wide variety of designs reveals amazing acceleration in proof times and is turning intractable problems provable in seconds. In case you couldn’t make it yesterday to the event watch the teaser. REGISTER YOUR INTEREST AT: https://lnkd.in/epg-8Sq9

Formal verification continues to prove, unequivocally, that it’s the only way to mathematically guarantee design correctness. In a recent #SemiconductorEngineering roundtable, "Advances in Formal Verification Technology," hosted by Brian Bailey, our CEO, Dr. Ashish Darbari, joined thought leaders from Cadence (Jin Zhang), Synopsys (Sean Safarpour), and Siemens EDA (Jeremy Levitt) to explore how the field is evolving faster than ever.   “Formal verification isn’t just about faster solvers, it’s about smarter modelling, effective property generation, and meaningful sign-off that ensures real silicon success.”   At Axiomise, we’ve been pioneering these advancements by focusing on:   ✅ Property generation: It involves bridging the gap between specifications and properties, handling complex designs, and reviewing the quality of generated properties. How do you take large, complex specifications and turn them into meaningful properties? Unless we start adopting formal methods in the functional verification space, by strengthening connections with specifications and making property generation faster and more efficient, we can’t make a significant impact with formal methods.   ✅ Refining constraints: It means writing simple, effective, and clear constraints and tying them back to the requirements specifications.   ✅ Debug: Making debugging effective and fast.   ✅ Proof convergence: Exploring how to go beyond bounded proofs and how abstraction and methodology contribute to proof convergence.   ✅ Sign-off and coverage: How do you holistically address the final aspects of the process to ensure that everything formally verified was done properly and that no bugs were left in the silicon?   The conversation reaffirmed that while computing power and AI help, true verification excellence comes from methodology and expertise.   As formal becomes mainstream across the semiconductor industry, we continue to lead with innovation, education, and trust, empowering teams to design with confidence, prove with precision, and verify with purpose.   🔗 Read the full discussion on Semiconductor Engineering: https://lnkd.in/ewq25TWJ

We are proud to be Silicon Sponsors of the largest #VLSI event in India. Looking forward to it!

Curiosity knows no boundaries. We were thrilled to see Dr Vidya Darbari, Co-founder and Director of Axiomise, speak at the #STEMBeyondBoundaries panel hosted by the University of Cambridge. Sharing the stage with experts from Xampla, the UK Government’s Department for Science, Innovation and Technology, Anovia Technology, and ERM Consulting, Vidya reflected on how, as a doctor, engineer, and scientist, she embodies the power of interdisciplinary thinking. Interdisciplinarity involves solving problems by combining the best ideas from multiple fields, including mathematics, physics, data science, and the life sciences. What matters most is the ability to learn and connect. At Axiomise, we live this philosophy every day, welcoming talent from all educational backgrounds and combining mathematics, engineering, and formal methods to make hardware design verification provably correct and reliable. #Innovation #Interdisciplinary #STEMCareers #Semiconductors #DiversityInSTEM #Makingformalnormal #Iloveformal

Wishing everyone a Happy Diwali!

Quiz Answer Revealed to this quiz 👉 Correct answer is B. Why? Read below! Want to go deeper? Explore our learning modules at https://lnkd.in/d_xi9sU #AxiomiseExplains #FormalVerification #LearningisFun #VerificationMadeSimple #Thinkformally

Looking to build a career in formal verification? Axiomise is hiring! Join us at these top career fairs and discover how you can be part of our mission to revolutionise hardware verification: 📍 Engineering & Tech Careers Fair 📍 Maths & Quants Fair 📍 IT, Science & Engineering Fair …and more! Meet our team, ask questions, and explore current opportunities. Visit https://www.axiomise.com/ #GraduateEngineeringJobs #AxiomiseCareers #JobOpportunities #WeAreHiring

Join our weekly #FunFormalVerificationQuiz and test your skills! Follow #Axiomise to get the correct answers and expert explanations every week. 💡 Learn more with our self-paced learning platform: 👉https://lnkd.in/eUdCjRc8 #WednesdayWithAxiomise #LearningNeverStops #AxiomiseQuiz #FormalVerification #LearningIsFun

In formal logic, “if, then” (→) and “if and only if” (↔) express key relationships. In programming, “if, then” is an if statement, while “if and only if” is written as (P → Q && Q → P). Understanding both helps bridge theory and practice in formal verification. At Axiomise, we make these concepts work for real-world designs. Want to see how formal logic powers real verification? 👉Explore our training programs: https://lnkd.in/eUdCjRc8 #Formalverification #Logic #Programming #Iloveformal #Math #Makingformalnormal

During Ashish Darbari’s Vision Talk at #DVConIndia2025, we were proud to officially unveil floatrix™ an end-to-end sign-off solution for floating-point hardware, fully integrated into our axiomiser® platform. 🔹 What floatrix™ Delivers: - Goldenised against Softfloat/Hardfloat - Comprehensive verification for FPUs in processors, GPUs and fancy AI/ML chips - Support for all number formats critical to AI/ML accelerators: FP64, FP32, FP16, bfloat16, FP8, FP4 - Efficient bug hunting & proof convergence using Axiomise abstraction models - Predictable run times to prove compliance with IEEE 754 - Verify custom floating-point designs - Intelligent debug & reporting with Scheduler and Reporter for Formal (SURF) With floatrix™, design teams can now catch corner-case bugs faster, achieve predictable verification closure, and sign off floating-point hardware with confidence. 👉 Want to learn more or see how floatrix™ can strengthen your verification flow? Get in touch with us today and let’s talk about making your floating-point hardware rock solid. https://lnkd.in/gW9Wjdvj #DVConIndia #FormalVerification #FloatingPoint #Floatrix #AI #ML #Processors #GPU