Pere G.

Synopsys Speed Adapters enable real hardware interaction during emulation, exposing critical design bugs. High-fidelity in-circuit emulation (ICE) exposes low-level system behavior issues, improving pre-silicon bug detection. Adoption of Synopsys speed adapters streamlines pre-silicon testing and reduces PHY programming/training time from months to weeks. Check out this article : https://lnkd.in/gtvWQ2Xe

129

Is There Still A Future For Hard Disk Drives? The cost of HDDs and SSDs will continue to fall, while capacity will continue to increase in both. The capacity for solid state drives (#SSDs) keeps going up while the price per terabyte keeps falling, sometimes raising questions about the future for hard disk drives (#HDDs). Will the cost of #SSDs per TB eventually become so low that they will totally displace HDDs? Barry Pangrle decided to ask a couple of experts in the field, Jim Handy from Objective Analysis and Thomas Coughlin of Coughlin Associates. He was looking for a comparison projection for HDDs and SSDs that would go about five years out into the future. Jim had performed such an exercise back in 2017, WDC: No SSD/HDD Crossover,but I needed something more recent. Jim had his SSD forecast data, shown in red in Figure 1 and Tom provided the HDD data shown in blue. The slope is steeper for the #SSD data, but it does not look like we’ll see a crossover in the next 5 years. The green $4.75/TB point was placed there by Barry to show readers where that falls on the plot and to use again later in another chart.... A very big thank you to Barry Pangrle , Jim Handy , Thomas Coughlin and Semiconductor Engineering for this very interesting full comparison/article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eKTxfR7P #semiconductorindustry #semiconductor #technology #tech #chip #chips #it #datacenter #technology #memory #storage #computer #ssd #hdd

88

4 Comments

The cost-effective QFN package is popular in Analog ICs, but parasitics of the wirebonds can be a challenge in some applications. This is particularly true for RF ICs and DC/DC switching converters. For these applications, the FlipChip QFN package provides a logical solution. By bumping the die and flipping it onto the leadframe, FlipChip QFN combines the benefits of a standard QFN - affordability and standardization - with enhanced electrical performance and a smaller footprint. In automotive applications, FlipChip QFN also offers the option of plated-end leads, which aid in solder fillet formation, further enhancing reliability. Amkor QFN Homepage: https://bit.ly/4dAzAhS

159

7 Comments

Another big milestone for Zero ASIC! Our Platypus family of open eFPGA just got a major upgrade in the relase of a set of heterogeneous eFPGAs with built in BRAM and DSP blocks. https://lnkd.in/e-HBARnG Platypus is the only eFPGA in the world guaranteeing: 100% open and standardized FPGA architectures 100% open source FPGA bitstream formats 100% open source FPGA development tools For the reasoning behind our open approach, check out the original Platypus announcement from earlier this year. https://lnkd.in/eyPxEUAX This awesome effort was led by Peter Grossmann, with tool chain contributions from Frederick Tombs, Wildebeest synthesis from Thierry Besson, and SiliconCompiler infrastructure from Peter Gadfort. With SoCs taking years to design and costing $100M - $1B to develop, I am always surprised more teams don't dedicate a portion of the silicon area to eFPGA logic. What's holding you back? Appreciate your thoughts and comments below.

528

26 Comments

🔍 The Formal Verification Cold Start Problem You’ve read the spec. You’ve discussed with the designer. You think you understand the design… But now you’re staring at a blank SVA file wondering: “Where do I even begin?” If that feels familiar, welcome to the cold start problem of formal verification—and yes, we’ve all been there. 💡 The Fix: Start with Cover Properties Forget trying to prove everything from day one. Your goal is to observe behavior before you start proving constraints. 🎯 Real Example: FIFO Design When I was verifying a simple synchronous FIFO, I started like this: cover property (@(posedge clk) wr_en && !full); ✅ Covers a write happening when FIFO isn’t full cover property (@(posedge clk) rd_en && !empty); ✅ Covers a read when FIFO isn’t empty cover property (@(posedge clk) wr_en ##[1:5] rd_en); ✅ Covers a write followed by a read within 5 cycles That’s it. From there, I built ordering checks, flag assertions, and finally full correctness proofs. The key was just starting. 🧪 Design Exercise Plan (for You or Your Team) Try this simple cold-start exercise on a FIFO design: 🔹 Step 1 – Cover Activity Cover a write when not full Cover a read when not empty Cover write followed by read 🔹 Step 2 – Observe State Cover full and empty being reached Cover FIFO staying non-empty for N cycles Cover pointer wraparound 🔹 Step 3 – Simple Assertions assert property: write only when not full assert property: read only when not empty assert: empty and full never both high 📌 Just like in software: don’t over-engineer your first line of code. In formal, don’t overthink your first property. Momentum matters more than perfection. Start anywhere. Learn as you go. #FormalVerification #VLSI #FIFO #SVA #SystemVerilog #DesignVerification #Semiconductors #HardwareDesign #VerificationEngineer #FormalMethods #ColdStartProblem #TechTips

107

6 Comments

Dear RF/Microwave Engineers, Today let me introduce another classic book from my bookshelf "Microwave Transistor Amplifiers Analysis and Design" by Guillermo Gonzalez. I don't think there is any RF/Microwave power amplifier designers (especially my contemporaries) who have not referred this book. This book can be read and understood by any RF designer. Very well written, in easy to read font size also 🙂, covering following topics: (1) Representation of two port networks (2) Microwave networks and signal flow graphs (3) Microwave transistor amplifier design (4) Noise, broadband, and high-power design networks (5) Microwave transistor oscillator design Appendix covers very useful concepts such as noise. This book will be very useful if you are going to design RF/ Microwave Amplifiers. Reading from hard copy is more enjoyable than from soft-copy of the book. It is classic book. Must have classic book in your book-shelf. Enjoy reading!

78

5 Comments

Yesterday, at DVCon U.S., Harry Foster (Siemens) shared some new results of his now traditional verification survey, showing that - in spite all the industry's efforts - the first-silicon-success dropped from 32% down to 14% in the last 4 years. And Ravi Subramanian (Synopsys) showed in his keynote how the compound complexity of AI chips - with challenges in size, power, memory, interconnect - changes everything! Are these two data points connected? With the increasing share of #AI chips in the #semiconductor pie, are there very new #verification challenges that need to be addressed? That will be the subject our panel today at DVCon U.S.! Looking forward to a great discussion with Harry Foster, Shuqing Zhao, Ahmad Ammar, Stuart Lindsay and Shahriar Seyedhosseini!

50

3 Comments

Exciting updates in the world of EDA and IP enablement! Intel Foundry has made significant strides with its PDK Tool Enablement Dashboard and IP Portfolio, showcasing robust support for 18A, 18A-P, and 14A/14A-E processes. Since early 2024, PDKs have been enabled with certification from five EDA partners (Ansys, Cadence, Keysight, Siemens, and Synopsys) and 29 tools, ensuring comprehensive coverage. The 14A/14A-E enablement is nearly complete, with just one module set to roll out later this quarter. On the IP front, the portfolio is ready to support customer design starts, featuring the latest technologies, including HBM4. From Foundation IP to high-speed SerDes and interface solutions like USB/USB PHY and UCIe PHY, Intel is poised to drive innovation forward. #IntelFoundry #EDA #IPEnablement #Semiconductor #Innovation #Technology #HBM4 #DesignEngineering - Intel Corporation - Intel Foundry - Cadence - Keysight Technologies - Siemens Electronic Systems Design & Manufacturing - Synopsys Inc

31