module DDS( input Clk, //系统时钟 input Rst_n, //系统复位 //input EN, //DDS模块使能 //input [31:0]Fword, //频率控制字 //input [11:0]Pword, //相位控制字 output DA_Clk, //DA数据输出时钟 output [7:0]DA_Data, //D输出输出A input FWORD_T_a , input FWORD_T_b , input PWORD_T_a , input PWORD_T_b ); reg [31:0]Fre_acc; reg [11:0]Rom_Addr; integer i = 0; reg [31:0]Fword = 32'd500; reg [11:0]Pword = 12'd0; /*---------------FPGA输入控制------------------*/ always @(posedge Clk or negedge Rst_n) begin if(!Rst_n) begin EN_T = 0; FWORD_T_a = 0; FWORD_T_b = 0; PWORD_T_a = 0; PWORD_T_b = 0; end else begin if(FWORD_T_a == 1) begin if(Fword <= 32'd1000&&Fword >= 32'd100 ) begin Fword <= Fword+32d'100; end end if(FWORD_T_b == 1) begin if(Fword <= 32'd1000&&Fword >= 32'd100 ) begin Fword<=Fword-32d'100; end end if(PWORD_T_a == 1) begin if(Pword <= 12'd4094&&Pword >= 12'd0 ) begin Pword <= Pword +12d'1024; end end if(PWORD_T_b == 1) begin if(Pword <= 12'd4094&&Pword >= 12'd0 ) begin Pword <= Pword - 12d'1024; end end end end /*---------------相位累加器------------------*/ always @(posedge Clk or negedge Rst_n) if(!Rst_n) Fre_acc <= 32'd0; else if(!EN) Fre_acc <= 32'd0; else Fre_acc <= Fre_acc + Fword; /*----------生成查找表地址---------------------*/ always @(posedge Clk or negedge Rst_n) if(!Rst_n) Rom_Addr <= 12'd0; else if(!EN) Rom_Addr <= 12'd0; else Rom_Addr <= Fre_acc[31:20] + Pword; /*----------例化查找表ROM-------*/ ROM ddsrom( .address(Rom_Addr), .clock(Clk), .q(DA_Data) ); /*----------输出DA时钟----------*/ assign DA_Clk = (EN)?Clk:1'b1; endmodule