module s_38( Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, A, B, C, Enable ); VERILOG
时间: 2024-02-15 22:48:09 浏览: 113
module s_38(
input Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, A, B, C, Enable,
output reg out
);
always @(*) begin
if (Enable) begin
case ({A,B,C})
3'b000: out = Y0;
3'b001: out = Y1;
3'b010: out = Y2;
3'b011: out = Y3;
3'b100: out = Y4;
3'b101: out = Y5;
3'b110: out = Y6;
3'b111: out = Y7;
endcase
end else begin
out = 1'b0;
end
end
endmodule
相关问题
module s_38( Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, A, B, C, Enable );
input Enable;
input [2:0] A, B, C;
output [7:0] Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7;
wire [7:0] temp_Y;
wire [2:0] temp_ABC;
// Multiplexer for selecting A, B, or C as input to decoder
assign temp_ABC = (Enable) ? A : (Enable) ? B : C;
// 3-to-8 decoder
decoder_3to8 d0 (temp_Y[0], temp_ABC[0], temp_ABC[1], temp_ABC[2]);
decoder_3to8 d1 (temp_Y[1], temp_ABC[0], temp_ABC[1], !temp_ABC[2]);
decoder_3to8 d2 (temp_Y[2], temp_ABC[0], !temp_ABC[1], temp_ABC[2]);
decoder_3to8 d3 (temp_Y[3], temp_ABC[0], !temp_ABC[1], !temp_ABC[2]);
decoder_3to8 d4 (temp_Y[4], !temp_ABC[0], temp_ABC[1], temp_ABC[2]);
decoder_3to8 d5 (temp_Y[5], !temp_ABC[0], temp_ABC[1], !temp_ABC[2]);
decoder_3to8 d6 (temp_Y[6], !temp_ABC[0], !temp_ABC[1], temp_ABC[2]);
decoder_3to8 d7 (temp_Y[7], !temp_ABC[0], !temp_ABC[1], !temp_ABC[2]);
// Assign outputs
assign {Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0} = temp_Y;
endmodule
// 3-to-8 Decoder module
module decoder_3to8 (Y, A, B, C);
output [7:0] Y;
input A, B, C;
assign Y[0] = !(A || B || C);
assign Y[1] = !(A || B || !C);
assign Y[2] = !(A || !B || C);
assign Y[3] = !(A || !B || !C);
assign Y[4] = !(!A || B || C);
assign Y[5] = !(!A || B || !C);
assign Y[6] = !(!A || !B || C);
assign Y[7] = !(!A || !B || !C);
endmodule
input A,B,C,Enable; output reg Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7; verilog
module eight_to_three_encoder(A,B,C,Enable,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7);
input A,B,C,Enable;
output reg Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7;
always @ (A,B,C,Enable) begin
if (Enable) begin
case ({A,B,C})
3'b000: begin Y0 = 1; Y1 = 0; Y2 = 0; Y3 = 0; Y4 = 0; Y5 = 0; Y6 = 0; Y7 = 0; end
3'b001: begin Y0 = 0; Y1 = 1; Y2 = 0; Y3 = 0; Y4 = 0; Y5 = 0; Y6 = 0; Y7 = 0; end
3'b010: begin Y0 = 0; Y1 = 0; Y2 = 1; Y3 = 0; Y4 = 0; Y5 = 0; Y6 = 0; Y7 = 0; end
3'b011: begin Y0 = 0; Y1 = 0; Y2 = 0; Y3 = 1; Y4 = 0; Y5 = 0; Y6 = 0; Y7 = 0; end
3'b100: begin Y0 = 0; Y1 = 0; Y2 = 0; Y3 = 0; Y4 = 1; Y5 = 0; Y6 = 0; Y7 = 0; end
3'b101: begin Y0 = 0; Y1 = 0; Y2 = 0; Y3 = 0; Y4 = 0; Y5 = 1; Y6 = 0; Y7 = 0; end
3'b110: begin Y0 = 0; Y1 = 0; Y2 = 0; Y3 = 0; Y4 = 0; Y5 = 0; Y6 = 1; Y7 = 0; end
3'b111: begin Y0 = 0; Y1 = 0; Y2 = 0; Y3 = 0; Y4 = 0; Y5 = 0; Y6 = 0; Y7 = 1; end
endcase
end
else begin
Y0 = 0; Y1 = 0; Y2 = 0; Y3 = 0; Y4 = 0; Y5 = 0; Y6 = 0; Y7 = 0;
end
end
endmodule
阅读全文
相关推荐
