函数uvm_component

### UVM Component Function Usage and Reference In the context of SystemVerilog, `uvm_component` is a fundamental building block within the Universal Verification Methodology (UVM). It serves as the base class for all components used in verification environments such as testbenches, agents, sequences, drivers, monitors, etc. Below are some commonly utilized functions associated with `uvm_component`. #### Common Functions of uvm_component The following list provides an overview of frequently-used methods: 1. **new() Constructor**: This method initializes the object instance. ```systemverilog function new(string name, uvm_component parent); super.new(name, parent); endfunction ``` 2. **build_phase(uvm_phase phase)**: Used to construct sub-components and configure them during the build process. ```systemverilog virtual function void build_phase(uvm_phase phase); super.build_phase(phase); // Call superclass implementation first // Example configuration code here... endfunction ``` 3. **connect_phase(uvm_phase phase)**: Connects ports between different components after they have been built but before simulation starts. ```systemverilog virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); // Always call this line first // Port connections go here... endfunction ``` 4. **end_of_elaboration_phase(uvm_phase phase)**: Provides information about elaborated hierarchy just prior to starting runtime phases like reset or main operations. ```systemverilog virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); // Debugging statements can be placed here... endfunction ``` 5. **run_phase(uvm_phase phase)**: Executes tasks that need continuous execution throughout most parts of the active portion of the testbench operation cycle. ```systemverilog task run_phase(uvm_phase phase); phase.raise_objection(this); // Raise objection so we stay in current state until done processing // Active processes happen inside loop below typically repeat(10) @(posedge clk); // Simulate activity over ten clock cycles #1ns; phase.drop_objection(this); // Drop our raised objections once finished executing desired actions endtask : run_phase ``` 6. **report_phase(uvm_phase phase)**: Summarizes results at conclusion point when entire sequence finishes running successfully without errors encountered along way. ```systemverilog virtual function void report_phase(uvm_phase phase); super.report_phase(phase); $display("Test completed."); endfunction ``` 7. **get_full_name(): string**: Returns full hierarchical path from root down through parents up till self included.[^1] 8. **set_report_verbosity_level_hier(int level)**: Sets verbosity levels hierarchically across multiple layers downwards recursively affecting child nodes too under same umbrella structure defined by user preferences set accordingly beforehand programmatically via script commands passed into environment setup scripts written specifically targeting particular use cases scenarios requiring customized settings tailored individually per project requirements basis case-by-case analysis performed iteratively continuously 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