module cm4_sync (// input clk,reset_n,d_async_i, // output q_o ); //---------------------------------------------------------------------------- // Parameters //---------------------------------------------------------------------------- parameter SYNC_PRESENT = 1; //---------------------------------------------------------------------------- // Port declarations //---------------------------------------------------------------------------- input clk; // Clock to which q_o will be synchronized input reset_n; // Reset for synchronization registers input d_async_i; // Signal to be synchronized output q_o; // Synchronized output `ifdef SYNTHESIS HDBULT06_SYNC2RBMSFQ_CAQY2M2_1 u_HDBULT06_SYNC2RBMSFQ_CAQY2M2_1(.Q(q_o), .CK(clk), .D(d_async_i), .RD(reset_n), .SI(1'b0), .SE(1'b0)); `else //---------------------------------------------------------------------------- // Signal Declarations //---------------------------------------------------------------------------- // Synchronization signals reg d_sync1; // 1st synchroniser DFF reg q; // 2nd synchroniser DFF // Optimization terms wire opt_q; //---------------------------------------------------------------------------- // Optimization terms //---------------------------------------------------------------------------- assign opt_q = (SYNC_PRESENT != 0) ? q : d_async_i; //---------------------------------------------------------------------------- // Synchronization //---------------------------------------------------------------------------- always @ (posedge clk or negedge reset_n) if (!reset_n) begin q <= 1'b0; d_sync1 <= 1'b0; end else begin q <= d_sync1; d_sync1 <= d_async_i; end //---------------------------------------------------------------------------- // Output assignments //---------------------------------------------------------------------------- assign q_o = opt_q; //---------------------------------------------------------------------------- // OVL assertions //---------------------------------------------------------------------------- `ifdef ARM_ASSERT_ON // Glitching input - valid waveform, but undesirable in handshake design. assert_never #(2,0, "Glitching input - valid waveform, but undesirable in handshake design.") ovl_cm4_sync_glitch(clk, reset_n, ((d_sync1 != d_async_i) & (d_sync1 != q))); // Input X not allowed - halt propogation at synchroniser level. assert_never_unknown #(0,1,0, "Input X not allowed - halt propogation at synchroniser level.") ovl_cm4_sync_xprop(clk, reset_n, 1'b1, d_async_i); `endif `endif endmodule 解释这段代码