verilog里case的用法

### SystemVerilog Case Statement Usage In SystemVerilog, the `case` statement provides a way to implement multiple-way branching based on an expression's value. The syntax of the `case` statement allows specifying several possible values for this expression and executing different blocks of code depending on which one matches. The general form of a `case` statement includes: - A controlling expression within parentheses. - One or more `case` items each consisting of a constant expression followed by a colon and statements to execute if the condition is met. - An optional default branch specified using `default:` keyword that handles all other cases not explicitly listed. #### Example 1: Basic Case Statement Here’s how a simple case structure looks like in practice: ```systemverilog module example_case ( input logic [2:0] sel, output logic y ); always_comb begin : proc_y unique case (sel) 3'b000: y = 1'b0; 3'b001: y = 1'b1; 3'b010: y = ~y; // This assumes initial value set elsewhere default: y = 1'bx; // For any unmatched inputs endcase end endmodule ``` This demonstrates basic usage where specific conditions lead directly to assignments without further nesting[^1]. #### Example 2: Using Inside Always Block With Reg Type Variables When implementing combinational logic inside an `always` block, variables should be declared as type `reg`. Blocking assignment (`=`) must be used instead of non-blocking (`<=`) because we want immediate evaluation during simulation rather than scheduling changes at the next time step[^3]. ```systemverilog module complex_case ( input wire clk, input wire reset_n, input wire [7:0] opcode, output reg result_valid ); always_ff @(posedge clk or negedge reset_n) begin : proc_result_valid if (!reset_n) begin result_valid <= 1'b0; end else begin case(opcode) 8'hFF: result_valid = 1'b1; 8'hAA: result_valid = ~(result_valid); // Toggle state default: result_valid = 1'b0; endcase end end endmodule ``` Note here that even though `opcode` might represent wires outside this module, internal signals such as `result_valid` are defined as registers due to being assigned within procedural constructs.

Verilog中的case语句用于根据一个或多个输入信号的不同值，执行相应的操作。case语句可以有多个分支，每个分支对应一个可能的输入值。下面是case语句的基本用法示例： ```verilog module example_module ( input wire [1:0] sel, output reg [3:0] out ); always @* begin case(sel) 2'b00: out = 4'b0000; 2'b01: out = 4'b0001; 2'b10: out = 4'b0010; 2'b11: out = 4'b0011; default: out = 4'bXXXX; // 默认值 endcase end endmodule ``` 在上面的示例中，根据输入信号`sel`的不同值，分别对`out`信号进行赋值。如果`sel`为`2'b00`，则将`out`赋值为`4'b0000`；如果`sel`为`2'b01`，则将`out`赋值为`4'b0001`，以此类推。如果输入信号的值没有匹配的分支，那么可以使用`default`关键字来定义一个默认的操作。