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module ad7091( input clock_i, input resetN_i, input clockSpi_i, input resetSpiN_i, input writeEnable_ip, input [11 : 0] writeAddress_i, input [31 : 0] writeData_i, input readEnable_ip, input [11 : 0] readAddress_i, output [31 : 0] readData_o, input adData_i, output adConvertN_o, output adSelectN_o, output adClock_o); //=========================================================================== localparam Timer200ms = 20000000; //=========================================================================== reg startAdConvert_r = 0; reg startAdConvertDelay0_r = 0; reg startAdConvertDelay1_r = 0; reg startAdRead_r = 0; reg startAdReadDelay0_r = 0; reg startAdReadDelay1_r = 0; reg [5 : 0] adClockDevideCounter_r = 0; reg [3 : 0] adClockCounter_r = 0; reg [11 : 0] adDataIn_r = 12'h000; reg adDataInPort_r = 0; reg adConvertN_r = 1'h1; reg adSelectN_r = 1'h1; reg adClock_r = 1'h0; //=========================================================================== assign readData_o[31 : 0] = {16'h0ff0, 4'hF, adDataIn_r[11 : 0]}; assign adConvertN_o = adConvertN_r; assign adSelectN_o = adSelectN_r; assign adClock_o = adClock_r; //=========================================================================== always @(posedge clock_i) begin if(resetN_i == 0) begin startAdConvert_r <= 0; startAdRead_r <= 0; end else begin if(writeEnable_ip == 1) begin case (writeAddress_i[11 : 0]) 12'h000: begin startAdConvert_r <= 1; end 12'h004: begin startAdConvert_r <= 0; end 12'h008: begin startAdRead_r <= 1; end 12'h00c: begin startAdRead_r <= 0; end default : begin end endcase end end end //=========================================================================== always @(posedge clock_i) begin startAdConvertDelay0_r <= startAdConvert_r; startAdConvertDelay1_r <= startAdConvertDelay0_r; startAdReadDelay0_r <= startAdRead_r; startAdReadDelay1_r <= startAdReadDelay0_r; if(resetN_i == 0) begin adDataInPort_r <= 0; adConvertN_r <= 1; adSelectN_r <= 1; adClock_r <= 1; adClockDevideCounter_r[5 : 0] <= 0; adClockCounter_r[3 : 0] <= 0; end else begin if((startAdConvertDelay0_r == 1) && (startAdConvertDelay1_r == 0)) begin adConvertN_r <= 0; end else if((startAdConvertDelay0_r == 0) && (startAdConvertDelay1_r == 1)) begin adConvertN_r <= 1; end if((startAdReadDelay0_r == 1) && (startAdReadDelay1_r == 0)) begin adSelectN_r <= 0; end else if((startAdReadDelay0_r == 0) && (startAdReadDelay1_r == 1)) begin adSelectN_r <= 1; end if(adSelectN_r == 0) begin adClockDevideCounter_r[5 : 0] <= adClockDevideCounter_r[5 : 0] + 1; if(adClockCounter_r[3 : 0] < 12) begin if(adClockDevideCounter_r[5 : 0] == (6'd15 - 1)) begin adDataIn_r[11 : 0] <= {adDataIn_r[10 : 0], adData_i}; adClock_r <= 0; end else if(adClockDevideCounter_r[5 : 0] >= (6'd30 - 1))begin adClockDevideCounter_r[5 : 0] <= 0; //adDataIn_r[11 : 0] <= {adDataIn_r[10 : 0], adData_i}; //adDataInPort_r <= adData_i; adClockCounter_r[3 : 0] <= adClockCounter_r[3 : 0] + 1; adClock_r <= 1; end end end else begin adClock_r <= 1; adClockDevideCounter_r[5 : 0] <= 0; adClockCounter_r[3 : 0] <= 0; end end end endmodule 和 module apb3_slave( input pClk_i, input pResetN_i, input pEnable_i, input pSel_i, input [11 : 0] pAddr_i, input pWrite_i, input [31 : 0] pWData_i, output [31 : 0] pRData_o, output pReady_o, output pSlverr_o, output writeEnable_op, output [11 : 0] writeAddress_o, output [31 : 0] writeData_o, output readEnable_op, output [11 : 0] readAddress_o, input [31 : 0] readData_i); //=========================================================================== reg pSlverr_r = 0; reg writeEnable_rp = 0; reg [11 : 0] pAddr_r = 0; reg [31 : 0] pWData_r = 0; reg readEnable_rp = 0; reg [11 : 0] pReadAddr_r = 0; //=========================================================================== assign writeEnable_op = writeEnable_rp; assign writeAddress_o[11 : 0] = pAddr_r[11 : 0]; assign writeData_o[31 : 0] = pWData_r[31 : 0]; assign readEnable_op = readEnable_rp; assign readAddress_o[11 : 0] = pReadAddr_r[11 : 0]; assign pRData_o[31 : 0] = readData_i[31 : 0]; assign pSlverr_o = pSlverr_r; assign pReady_o = 1; //=========================================================================== always @(posedge pClk_i) begin if(pResetN_i == 0) begin pSlverr_r <= 0; writeEnable_rp <= 0; pAddr_r[11 : 0] <= 12'h000; pWData_r[31 : 0] <= 32'h0000_0000; end else begin writeEnable_rp <= 0; if((pSel_i == 1) && (pEnable_i == 1) && (pWrite_i == 1)) begin //pAddr_r[11 : 0] <= pAddr_i[11 : 0]; pAddr_r[11 : 0] <= {4'h0, pAddr_i[7 : 0]}; pWData_r[31 : 0] <= pWData_i[31 : 0]; writeEnable_rp <= 1; end end end //=========================================================================== always @(posedge pClk_i) begin if(pResetN_i == 0) begin readEnable_rp <= 0; pReadAddr_r[11 : 0] <= 12'h000; end else begin readEnable_rp <= 0; if((pSel_i == 1) && (pWrite_i == 0) && (pEnable_i == 0)) begin //pReadAddr_r[11 : 0] <= pAddr_i[11 : 0]; pReadAddr_r[11 : 0] <= {4'h0, pAddr_i[7 : 0]}; readEnable_rp <= 1; end end end //=========================================================================== endmodule 和 module apb3_slave_16bits( input pClk_i, input pResetN_i, input pEnable_i, input pSel_i, input [15 : 0] pAddr_i, input pWrite_i, input [31 : 0] pWData_i, output [31 : 0] pRData_o, output pReady_o, output pSlverr_o, output writeEnable_op, output [15 : 0] writeAddress_o, output [31 : 0] writeData_o, output readEnable_op, output [15 : 0] readAddress_o, input [31 : 0] readData_i); //=========================================================================== reg pSlverr_r = 0; reg writeEnable_rp = 0; reg [15 : 0] pAddr_r = 0; reg [31 : 0] pWData_r = 0; reg readEnable_rp = 0; reg [15 : 0] pReadAddr_r = 0; //=========================================================================== assign writeEnable_op = writeEnable_rp; assign writeAddress_o[15 : 0] = pAddr_r[15 : 0]; assign writeData_o[31 : 0] = pWData_r[31 : 0]; assign readEnable_op = readEnable_rp; assign readAddress_o[15 : 0] = pReadAddr_r[15 : 0]; assign pRData_o[31 : 0] = readData_i[31 : 0]; assign pSlverr_o = pSlverr_r; assign pReady_o = 1; //=========================================================================== always @(posedge pClk_i) begin if(pResetN_i == 0) begin pSlverr_r <= 0; writeEnable_rp <= 0; pAddr_r[15 : 0] <= 16'h0000; pWData_r[31 : 0] <= 32'h0000_0000; end else begin writeEnable_rp <= 0; if((pSel_i == 1) && (pEnable_i == 1) && (pWrite_i == 1)) begin //pAddr_r[11 : 0] <= pAddr_i[11 : 0]; pAddr_r[15 : 0] <= {4'h0, pAddr_i[11 : 0]}; pWData_r[31 : 0] <= pWData_i[31 : 0]; writeEnable_rp <= 1; end end end //=========================================================================== always @(posedge pClk_i) begin if(pResetN_i == 0) begin readEnable_rp <= 0; pReadAddr_r[15 : 0] <= 16'h0000; end else begin readEnable_rp <= 0; if((pSel_i == 1) && (pWrite_i == 0) && (pEnable_i == 0)) begin //pReadAddr_r[11 : 0] <= pAddr_i[11 : 0]; pReadAddr_r[15 : 0] <= {4'h0, pAddr_i[11 : 0]}; readEnable_rp <= 1; end end end //=========================================================================== endmodule 和 /* clock_i is bus clock / module can( input clock_i, input resetN_i, input writeEnable_ip, input [15 : 0] writeAddress_i, input [31 : 0] writeData_i, input readEnable_ip, input [15 : 0] readAddress_i, output [31 : 0] readData_o, output interrupt_o, inout [7 : 0] ad_Pad, output ale_pad_o, output csn_Pad_o, output rdn_Pad_o, output wrn_Pad_o, input intn_Pad_i); //=========================================================================== localparam [3 : 0] IS0 = 4'h0, IS1 = 4'h1, IS2 = 4'h2, IS3 = 4'h3, IS4 = 4'h4, IS5 = 4'h5; localparam [3 : 0] TS0 = 4'h0, TS1 = 4'h1, TS2 = 4'h2, TS3 = 4'h3, TS4 = 4'h4, TS5 = 4'h5, TS6 = 4'h6, TS7 = 4'h7, TS8 = 4'h8, TS9 = 4'h9, TS10 = 4'ha, TS11 = 4'hb, TS12 = 4'hc, TS13 = 4'hd, TS14 = 4'he; //=========================================================================== reg [31 : 0] canControl_r = 0; reg [3 : 0] canControlState_r = IS0; reg [3 : 0] canInterfaceDelayCounter_r = 0; reg [7 : 0] canRegAddress_r = 0; reg [7 : 0] canRegNumber_r = 0; reg [31 : 0] canWriteDataBuffer_r [3 : 0]; reg [31 : 0] canReadDataBuffer_r [3 : 0]; reg startOneTransmit_rp = 0; reg endOneTransmit_rp = 0; reg startOneRead_rp = 0; reg endOneRead_rp = 0; reg [3 : 0] canTransmitState_r = TS0; reg [31 : 0] adPreOut_r = 0; reg ale_r = 0; reg csN_r = 1; reg rdn_r = 1; reg wrn_r = 1; reg [7 : 0] adIn_r = 0; reg [7 : 0] adOut_r = 0; reg adOutEnable_r = 1; reg interrupt_r = 0; reg intn_r = 1; //=========================================================================== reg [31 : 0] readData_rw; //=========================================================================== assign readData_o[31 : 0] = readData_rw[31 : 0]; assign interrupt_o = interrupt_r; assign ad_Pad[7 : 0] = (adOutEnable_r == 1) ? adOut_r[7 : 0] : 8'hzz; assign ale_pad_o = ale_r; assign csn_Pad_o = csN_r; assign rdn_Pad_o = rdn_r; assign wrn_Pad_o = wrn_r; //=========================================================================== always @(readAddress_i[15 : 0], canReadDataBuffer_r[0], canReadDataBuffer_r[1], canReadDataBuffer_r[2], canReadDataBuffer_r[3], canControl_r[31 : 0], canControlState_r[3 : 0], canTransmitState_r[3 : 0]) begin case (readAddress_i[15 : 0]) 16'h0000 : readData_rw[31 : 0] = canReadDataBuffer_r[0]; 16'h0004 : readData_rw[31 : 0] = canReadDataBuffer_r[1]; 16'h0008 : readData_rw[31 : 0] = canReadDataBuffer_r[2]; 16'h000c : readData_rw[31 : 0] = canReadDataBuffer_r[3]; 16'h0010 : readData_rw[31 : 0] = canControl_r[31 : 0]; 16'h0014 : readData_rw[31 : 0] = {intn_r, 7'h00, 8'h00, 8'h00, canTransmitState_r[3 : 0], canControlState_r[3 : 0]}; default : readData_rw[31 : 0] = 32'h0000_0000; endcase end //=========================================================================== always @(posedge clock_i) begin if((writeEnable_ip == 1) && (writeAddress_i[15 : 4] == 8'h00)) begin canWriteDataBuffer_r[writeAddress_i[3 : 2]] <= writeData_i[31 : 0]; end end //=========================================================================== always @(posedge clock_i) begin if(resetN_i == 0) begin canInterfaceDelayCounter_r[3 : 0] <= 0; canControl_r[31 : 0] <= 0; startOneTransmit_rp <= 0; startOneRead_rp <= 0; canControlState_r[3 : 0] <= IS0; end else begin canInterfaceDelayCounter_r[3 : 0] <= canInterfaceDelayCounter_r[3 : 0] + 1; startOneTransmit_rp <= 0; startOneRead_rp <= 0; case (canControlState_r[3 : 0]) IS0 : begin if((writeEnable_ip == 1) && (writeAddress_i[15 : 0] == 12'h010)) begin canControl_r[31 : 0] <= writeData_i[31 : 0]; canRegNumber_r[7 : 0] <= 0; canControlState_r[3 : 0] <= IS1; end end IS1 : begin canInterfaceDelayCounter_r[3 : 0] <= 0; if(canControl_r[0] == 1) begin //write startOneTransmit_rp <= 1; canControlState_r[3 : 0] <= IS2; end else if(canControl_r[1] == 1) begin //read startOneRead_rp <= 1; canControlState_r[3 : 0] <= IS4; end else begin canControlState_r[3 : 0] <= IS0; end end IS2 : begin if(endOneTransmit_rp == 1) begin canRegNumber_r[7 : 0] <= canRegNumber_r[7 : 0] + 1; canControlState_r[3 : 0] <= IS3; end end IS3 : begin if(canRegNumber_r[7 : 0] >= canControl_r[23 : 16]) begin canControl_r[0] <= 0; canControlState_r[3 : 0] <= IS0; end else begin startOneTransmit_rp <= 1; canControlState_r[3 : 0] <= IS2; end end IS4 : begin if(endOneRead_rp == 1) begin canRegNumber_r[7 : 0] <= canRegNumber_r[7 : 0] + 1; canControlState_r[3 : 0] <= IS5; end end IS5 : begin if(canRegNumber_r[7 : 0] >= canControl_r[23 : 16]) begin canControl_r[1] <= 0; canControlState_r[3 : 0] <= IS0; end else begin startOneRead_rp <= 1; canControlState_r[3 : 0] <= IS4; end end default : begin canInterfaceDelayCounter_r[3 : 0] <= 0; canControl_r[31 : 0] <= 0; startOneTransmit_rp <= 0; startOneRead_rp <= 0; canControlState_r[3 : 0] <= IS0; end endcase end end //=========================================================================== always @(posedge clock_i) begin if(resetN_i == 0) begin ale_r <= 0; csN_r <= 1; wrn_r <= 1; rdn_r <= 1; endOneTransmit_rp <= 0; adOutEnable_r <= 1; endOneRead_rp <= 0; canTransmitState_r[3 : 0] <= TS0; end else begin endOneTransmit_rp <= 0; endOneRead_rp <= 0; case (canTransmitState_r[3 : 0]) TS0 : begin adOutEnable_r <= 1; csN_r <= 1; if(startOneTransmit_rp == 1) begin canTransmitState_r[3 : 0] <= TS1; end else if(startOneRead_rp == 1) begin canTransmitState_r[3 : 0] <= TS8; end end TS1 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin ale_r <= 1; adPreOut_r[31 : 0] <= canWriteDataBuffer_r[canRegNumber_r[3 : 2]]; canTransmitState_r[3 : 0] <= TS2; end end TS2 : begin adOut_r[7 : 0] <= canControl_r[15 : 8] + canRegNumber_r[7 : 0]; canTransmitState_r[3 : 0] <= TS3; end TS3 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin ale_r <= 0; canTransmitState_r[3 : 0] <= TS4; end end TS4 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hd) begin csN_r <= 0; end if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin wrn_r <= 0; canTransmitState_r[3 : 0] <= TS5; end end TS5 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin case (canRegNumber_r[1 : 0]) 2'h0 : adOut_r[7 : 0] <= adPreOut_r[7 : 0]; 2'h1 : adOut_r[7 : 0] <= adPreOut_r[15 : 8]; 2'h2 : adOut_r[7 : 0] <= adPreOut_r[23 : 16]; 2'h3 : adOut_r[7 : 0] <= adPreOut_r[31 : 24]; default : adOut_r[7 : 0] <= 0; endcase canTransmitState_r[3 : 0] <= TS6; end end TS6 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin wrn_r <= 1; canTransmitState_r[3 : 0] <= TS7; end end TS7 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'h2) begin csN_r <= 1; end if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin endOneTransmit_rp <= 1; canTransmitState_r[3 : 0] <= TS0; end end TS8 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin ale_r <= 1; canTransmitState_r[3 : 0] <= TS9; end end TS9 : begin adOut_r[7 : 0] <= canControl_r[15 : 8] + canRegNumber_r[7 : 0]; canTransmitState_r[3 : 0] <= TS10; end TS10 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin ale_r <= 0; canTransmitState_r[3 : 0] <= TS11; end end TS11 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hd) begin csN_r <= 0; end if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin adOutEnable_r <= 0; rdn_r <= 0; canTransmitState_r[3 : 0] <= TS12; end end TS12 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin canTransmitState_r[3 : 0] <= TS13; end end TS13 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin adIn_r[7 : 0] <= ad_Pad[7 : 0]; rdn_r <= 1; canTransmitState_r[3 : 0] <= TS14; end end TS14 : begin if(canInterfaceDelayCounter_r[3 : 0] == 4'h2) begin csN_r <= 0; end if(canInterfaceDelayCounter_r[3 : 0] == 4'hf) begin adOutEnable_r <= 1; endOneRead_rp <= 1; case (canRegNumber_r[1 : 0]) 2'h0 : canReadDataBuffer_r[canRegNumber_r[3 : 2]][7 : 0] <= adIn_r[7 : 0]; 2'h1 : canReadDataBuffer_r[canRegNumber_r[3 : 2]][15 : 8] <= adIn_r[7 : 0]; 2'h2 : canReadDataBuffer_r[canRegNumber_r[3 : 2]][23 : 16] <= adIn_r[7 : 0]; 2'h3 : canReadDataBuffer_r[canRegNumber_r[3 : 2]][31 : 24] <= adIn_r[7 : 0]; endcase canTransmitState_r[3 : 0] <= TS0; end end default : begin ale_r <= 0; csN_r <= 1; wrn_r <= 1; rdn_r <= 1; endOneTransmit_rp <= 0; adOutEnable_r <= 1; endOneRead_rp <= 0; canTransmitState_r[3 : 0] <= TS0; end endcase end end //=========================================================================== always @(posedge clock_i) begin if(resetN_i == 0) begin intn_r <= 1; interrupt_r <= 0; end else begin intn_r <= intn_Pad_i; if(intn_r == 0) begin interrupt_r <= 1; end else begin interrupt_r <= 0; end //else if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h010) && (writeData_i[2] == 1)) begin // interrupt_r <= 0; //end end end endmodule 和 / clock_i is 120MHz / module encoder( input clock_i, input resetN_i, input writeEnable_ip, input [11 : 0] writeAddress_i, input [31 : 0] writeData_i, input readEnable_ip, input [11 : 0] readAddress_i, output [31 : 0] readData_o, output interrupt_o, output encoderOutTest_o, output clock_o, input encoderData_i); //======================================================= parameter [3 : 0] State0 = 4'h0, State1 = 4'h1, State2 = 4'h2, State3 = 4'h3, State4 = 4'h4, State5 = 4'h5, State6 = 4'h6, State7 = 4'h7; //======================================================= reg [6 : 0] clockCounter_r = 0; reg clockPosedge_r = 0; reg encoderDataValid_r = 0; reg encoderCrcErrorOut_r = 0; reg encoderCommunicateErrorOut_r = 0; reg readEncoderPosition_r = 0; ( IOB="TRUE" ) reg clock_r = 0; reg [5 : 0] crcCheckBits_r = 0; reg [5 : 0] crcCheck_r = 0; reg encoderData_r = 1; reg [27 : 0] encoderDataCatch_r = 0; reg [7 : 0] encoderDataCheckCounter_r = 0; ( FSM_ENCODING="USER" ) reg [3 : 0] crcCheckState_r = State0; //======================================================= assign readData_o[31 : 0] = {encoderCommunicateErrorOut_r, encoderCrcErrorOut_r, 2'h0, encoderDataCatch_r[27 : 0]}; assign interrupt_o = encoderDataValid_r; assign clock_o = clock_r; assign encoderOutTest_o = encoderData_r; //======================================================= always @(posedge clock_i) begin if(resetN_i == 0) begin readEncoderPosition_r <= 0; end else begin if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h000) && (writeData_i[0] ==1'h1)) begin readEncoderPosition_r <= 1; end else if(encoderDataValid_r == 1) begin readEncoderPosition_r <= 0; end end end //======================================================= always @(posedge clock_i) begin if(resetN_i == 0) begin clockCounter_r[6 : 0] <= 0; clock_r <= 1; end else begin if(readEncoderPosition_r == 1'h0) begin clockCounter_r[6 : 0] <= 0; clock_r <= 1'h1; end else begin clockCounter_r[6 : 0] <= clockCounter_r[6 : 0] + 1; clock_r <= clockCounter_r[6]; end end end always @(posedge clock_i) begin if((clockCounter_r[6 : 0] == 7'h3f)) begin clockPosedge_r <= 1'h1; encoderData_r <= encoderData_i; end else begin clockPosedge_r <= 1'h0; end end always @(posedge clock_i) begin if(resetN_i == 0) begin encoderDataValid_r <= 0; encoderCrcErrorOut_r <= 0; encoderCommunicateErrorOut_r <= 0; encoderDataCatch_r[27 : 0] <= 0; crcCheckState_r[3 : 0] <= State0; end else begin if((readEnable_ip == 1) && (readAddress_i[11 : 0] == 12'h000)) begin encoderDataValid_r <= 0; end else begin case (crcCheckState_r[3 : 0]) State0 : begin if((readEncoderPosition_r == 1'h1) && (clockPosedge_r == 1'h1)) begin if(encoderData_r == 1'h0) begin //ACK SIGNAL encoderDataCheckCounter_r[7 : 0] <= 0; crcCheckState_r[3 : 0] <= State1; end else begin encoderDataCheckCounter_r[7 : 0] <= encoderDataCheckCounter_r[7 : 0] + 1; if(encoderDataCheckCounter_r[7 : 0] == 8'hff) begin encoderCommunicateErrorOut_r <= 1'h1; encoderDataValid_r <= 1; crcCheckState_r[3 : 0] <= State6; end end end end State1 : begin if(clockPosedge_r == 1'h1) begin if(encoderData_r == 1'h1) begin //START SIGNAL encoderDataCheckCounter_r[7 : 0] <= 0; crcCheckState_r[3 : 0] <= State2; end else begin encoderDataCheckCounter_r[7 : 0] <= encoderDataCheckCounter_r[7 : 0] + 1; if(encoderDataCheckCounter_r[7 : 0] == 8'hff) begin encoderCommunicateErrorOut_r <= 1'h1; encoderDataValid_r <= 1; crcCheckState_r[3 : 0] <= State6; end end end end State2 : begin if(clockPosedge_r == 1'h1) begin if(encoderData_r == 1'h0) begin //0 SYNC SIGNAL encoderDataCheckCounter_r[7 : 0] <= 0; crcCheckBits_r[5 : 0] <= 0; crcCheckState_r[3 : 0] <= State3; end else begin encoderDataCheckCounter_r[7 : 0] <= encoderDataCheckCounter_r[7 : 0] + 1; if(encoderDataCheckCounter_r[7 : 0] == 8'hff) begin encoderCommunicateErrorOut_r <= 1'h1; encoderDataValid_r <= 1; crcCheckState_r[3 : 0] <= State6; end end end end State3 : begin if(clockPosedge_r == 1'h1) begin //POSITION SIGNAL encoderDataCatch_r[27 : 0] <= {encoderDataCatch_r[26 : 0], encoderData_r}; encoderDataCheckCounter_r[7 : 0] <= encoderDataCheckCounter_r[7 : 0] + 1'h1; if(encoderDataCheckCounter_r[7 : 0] == 27) begin encoderDataCheckCounter_r[7 : 0] <= 0; crcCheckState_r[3 : 0] <= State4; end crcCheckBits_r[0] <= encoderData_r ^ crcCheckBits_r[5]; crcCheckBits_r[1] <= crcCheckBits_r[0] ^ (encoderData_r ^ crcCheckBits_r[5]); crcCheckBits_r[2] <= crcCheckBits_r[1]; crcCheckBits_r[3] <= crcCheckBits_r[2]; crcCheckBits_r[4] <= crcCheckBits_r[3]; crcCheckBits_r[5] <= crcCheckBits_r[4]; end end State4 : begin if(clockPosedge_r == 1'h1) begin //CRC SIGNAL crcCheck_r[5 : 0] <= {crcCheck_r[4 : 0], encoderData_r}; encoderDataCheckCounter_r[7 : 0] <= encoderDataCheckCounter_r[7 : 0] + 1'h1; if(encoderDataCheckCounter_r[7 : 0] == 5) begin crcCheckBits_r[5 : 0] <= ~crcCheckBits_r[5 : 0]; crcCheckState_r[3 : 0] <= State5; end end end State5 : begin encoderDataCheckCounter_r[7 : 0] <= 0; if(crcCheckBits_r[5 : 0] == crcCheck_r[5 : 0]) begin encoderCrcErrorOut_r <= 1'h0; end else begin encoderCrcErrorOut_r <= 1'h1; end encoderDataValid_r <= 1; crcCheckState_r[3 : 0] <= State6; end State6 : begin if(encoderDataValid_r == 0) begin crcCheckState_r[3 : 0] <= State7; end end State7 : begin encoderCrcErrorOut_r <= 1'h0; encoderCommunicateErrorOut_r <= 0; //encoderDataCheckCounter_r[7 : 0] <= encoderDataCheckCounter_r[7 : 0] + 1; //if(encoderDataCheckCounter_r[7] == 1'h1) begin //encoderDataCheckCounter_r[7 : 0] <= 0; crcCheckState_r[3 : 0] <= State0; //end end default : begin encoderDataValid_r <= 0; encoderCrcErrorOut_r <= 0; encoderCommunicateErrorOut_r <= 0; crcCheckState_r[3 : 0] <= State0; end endcase end end end endmodule 和 module heater( input clock_i, input resetN_i, input writeEnable_ip, input [11 : 0] writeAddress_i, input [31 : 0] writeData_i, input readEnable_ip, input [11 : 0] readAddress_i, output [31 : 0] readData_o, output [11 : 0] heaterPad_o, input [11 : 0] heaterPad_i); //=========================================================================== localparam Timer200ms = 20000000; //=========================================================================== reg [11 : 0] heaterPad_r = 12'h000; reg [11 : 0] heaterPadLatched_r = 12'h000; //=========================================================================== assign readData_o[31 : 0] = {16'h0000, 4'h0, heaterPadLatched_r[11 : 0]}; assign heaterPad_o[11 : 0] = heaterPad_r[11 : 0]; //=========================================================================== always @(posedge clock_i) begin heaterPadLatched_r[11 : 0] <= heaterPad_i[11 : 0]; if(resetN_i == 0) begin heaterPad_r[11 : 0] <= 12'h000; end else begin if(writeEnable_ip == 1) begin case (writeAddress_i[11 : 0]) 12'h000: begin heaterPad_r[11 : 0] <= writeData_i[11 : 0]; end default : begin end endcase end end end //=========================================================================== endmodule 和 module motor( input clock_i, //120M input resetN_i, input writeEnable_ip, input [11 : 0] writeAddress_i, input [31 : 0] writeData_i, input readEnable_ip, input [11 : 0] readAddress_i, output [31 : 0] readData_o, output interrupt_o, output motorResetN_o, output motorEnableN_o, output motorSleepN_o, output motorStep_o, output motorDirection_o); //======================================================= localparam [2 : 0] MS0 = 3'h0, MS1 = 3'h1, MS2 = 3'h2, MS3 = 3'h3, MS4 = 3'h4, MS5 = 3'h5, MS6 = 3'h6, MS7 = 3'h7; //======================================================= reg [15 : 0] clockDivdeNumer_r = 16'd12000; reg [15 : 0] clockCounter_r = 0; reg motorResetN_r = 0; reg motorStep_r = 0; reg motorEnableN_r = 1; reg motorSleepN_r = 0; reg [15 : 0] motorDelayCounter_r = 0; reg [15 : 0] motorStepsCounter_r = 0; reg [15 : 0] motorTargetSteps_r = 0; reg motorTargetDirection_r = 0; reg interrupt_r = 0; reg driveUpdate_rp = 0; reg motorStop_rp = 0; reg motorMoveEnd_rp = 0; ( FSM_ENCODING="USER" *) reg [2 : 0] motorDriveState_r = MS0; //======================================================= assign readData_o[31 : 0] = {motorStepsCounter_r[15 : 0], 13'h0000, motorDriveState_r[2 : 0]}; assign interrupt_o = interrupt_r; assign motorResetN_o = motorResetN_r; assign motorEnableN_o = motorEnableN_r; assign motorSleepN_o = motorSleepN_r; assign motorStep_o = motorStep_r; assign motorDirection_o = motorTargetDirection_r; //======================================================= always @(posedge clock_i) begin if((resetN_i == 0) || (driveUpdate_rp == 1)) begin clockCounter_r[15 : 0] <= 0; end else begin clockCounter_r[15 : 0] <= clockCounter_r[15 : 0] + 1; if(clockCounter_r[15 : 0] == (clockDivdeNumer_r[15 : 0] - 1)) begin clockCounter_r[15 : 0] <= 0; end end end //======================================================= always @(posedge clock_i) begin if(resetN_i == 0) begin motorResetN_r <= 0; driveUpdate_rp <= 0; clockDivdeNumer_r[15 : 0] <= 16'd12000; end else begin driveUpdate_rp <= 0; motorStop_rp <= 0; if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h000)) begin motorTargetSteps_r[15 : 0] <= writeData_i[15 : 0]; motorTargetDirection_r <= writeData_i[16]; end else if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h004)) begin clockDivdeNumer_r[15 : 0] <= writeData_i[15 : 0]; end else if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h008)) begin driveUpdate_rp <= 1; end else if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h00c)) begin motorResetN_r <= 1; end else if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h010)) begin motorResetN_r <= 0; end else if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h014)) begin motorStop_rp <= 1; end else if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h018)) begin //motor enable // motorEnableN_r <= 0; // motorSleepN_r <= 1; end else if((writeEnable_ip == 1) && (writeAddress_i[11 : 0] == 12'h01c)) begin //motor disable // motorEnableN_r <= 1; // motorSleepN_r <= 0; end end end always @(posedge clock_i) begin if((resetN_i == 0) || (motorStop_rp == 1)) begin motorDelayCounter_r[15 : 0] <= 0; motorStep_r <= 0; motorEnableN_r <= 1; motorSleepN_r <= 0; motorDriveState_r[2 : 0] <= MS0; end else begin motorMoveEnd_rp <= 0; case(motorDriveState_r[2 : 0]) MS0 : begin if(driveUpdate_rp == 1) begin motorDelayCounter_r[15 : 0] <= 0; motorStepsCounter_r[15 : 0] <= 0; motorEnableN_r <= 0; motorSleepN_r <= 1; motorDriveState_r[2 : 0] <= MS1; end end MS1 : begin motorDelayCounter_r[15 : 0] <= motorDelayCounter_r[15 : 0] + 1; if(motorDelayCounter_r[15 : 0] >= 16'd200000) begin motorDelayCounter_r[15 : 0] <= 0; motorDriveState_r[2 : 0] <= MS2; end end MS2 : begin if(clockCounter_r[15 : 0] == (clockDivdeNumer_r[15 : 0] - 1)) begin motorStepsCounter_r[15 : 0] <= motorStepsCounter_r[15 : 0] + 1; motorStep_r <= 1; motorDriveState_r[2 : 0] <= MS3; end end MS3 : begin if(clockCounter_r[15 : 0] == (clockDivdeNumer_r[15 : 0] - 1)) begin motorStep_r <= 0; if(motorStepsCounter_r[15 : 0] >= motorTargetSteps_r[15 : 0]) begin motorDelayCounter_r[15 : 0] <= 0; motorMoveEnd_rp <= 1; motorDriveState_r[2 : 0] <= MS4; end else begin motorDriveState_r[2 : 0] <= MS2; end end end MS4 : begin motorDelayCounter_r[15 : 0] <= motorDelayCounter_r[15 : 0] + 1; if(motorDelayCounter_r[15 : 0] >= 16'd200000) begin motorDelayCounter_r[15 : 0] <= 0; motorEnableN_r <= 1; motorSleepN_r <= 0; motorDriveState_r[2 : 0] <= MS0; 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matlab app designer中 如何打开并保存demo1.mat文件中的ts8.m文件和class.m文件

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matlab appdesigner中如何使用一个按钮打开并保存demo1.mat文件中的ts8.m文件和class.m文件

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matlab appdesigner中如何使用一个按钮打开并保存特定路径的demo1.mat文件中的ts8.m文件和class.m文件

matlab appdesigner中如何使用一个按钮打开特定路径的demo1.mat文件中的ts8.m向量和class.m向量，并将这两个向量的值赋值给两个变量

matlab appdesigner中如何使用一个按钮打开特定路径的demo1.mat文件中的ts8.m向量和class8.m向量，并将这两个向量的值赋值给两个变量

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