在Vitis 中的project FPGA 中添加比特流文件 报错 ERROR: Could not find 64-bit executable. ERROR: D:/FPGA_software/Vivado/Vitis/2019.2/bin/unwrapped/win64.o/data2mem.exe does not exist

时间: 2025-07-26 10:21:37 浏览: 14
<think>我们正在处理一个关于Vitis FPGA项目中添加比特流文件时出现的错误问题。错误信息是:“Could not find 64-bit executable data2mem.exe missing”。根据这个错误,我们知道Vitis在尝试使用data2mem工具时,找不到64位版本的可执行文件。 首先,我们需要了解data2mem工具的作用。data2mem是Xilinx工具链中的一个实用程序,用于将数据文件合并到比特流中,通常用于初始化块RAM(BRAM)的内容。这个工具在Vitis中用于将软件代码(如ELF文件)合并到硬件比特流中,从而生成一个包含软件的完整比特流文件。 错误信息明确指出找不到64位的data2mem.exe。这可能是因为: 1. 该工具未正确安装。 2. 环境变量设置问题,导致Vitis无法找到该工具。 3. 安装的Vitis版本不完整或损坏。 ### 解决步骤 #### 1. 确认工具是否存在 首先,我们需要检查Vitis安装目录下是否存在`data2mem.exe`。通常,它位于以下路径(假设Vitis安装在`C:\Xilinx`): ``` C:\Xilinx\Vitis\<version>\bin\data2mem.exe ``` 注意:`<version>`是Vitis的版本号,例如`2020.2`。 同时,注意64位可执行文件通常位于`bin`目录下,而32位版本可能在`bin\win64`或其他子目录中。但根据错误信息,我们需要64位版本。 如果在该路径下找不到`data2mem.exe`,则可能是安装不完整。 #### 2. 重新安装或修复安装 如果确认没有该文件,可以尝试重新安装Vitis或修复安装。在安装过程中,确保选择了所有必要的组件,特别是与FPGA开发相关的工具。 #### 3. 检查环境变量 如果文件存在,那么可能是环境变量没有正确设置。Vitis需要知道其工具链的路径。通常,安装程序会自动设置环境变量,但有时可能会被覆盖或修改。 检查系统环境变量中是否有`XILINX_VITIS`和`XILINX_VIVADO`(因为Vitis依赖于Vivado),并且它们的路径指向正确的安装目录。同时,确保`PATH`环境变量中包含了Vitis的`bin`目录。 例如,在Windows系统中,`PATH`应该包含: ``` C:\Xilinx\Vitis\<version>\bin ``` #### 4. 使用Vivado的data2mem 有时,`data2mem.exe`可能位于Vivado的安装目录下,而不是Vitis。因为Vitis和Vivado共享一些工具。检查Vivado的安装目录: ``` C:\Xilinx\Vivado\<version>\bin\data2mem.exe ``` 如果在这里找到了,那么可以将这个路径添加到系统的`PATH`环境变量中,或者将文件复制到Vitis的`bin`目录下。 #### 5. 更新Vitis版本 如果使用的是较旧的Vitis版本,可能会存在已知的问题。尝试更新到最新版本。 #### 6. 手动下载 如果上述方法都不行,可以尝试从Xilinx官方网站下载`data2mem`工具(如果提供的话)或从其他正常安装的机器上复制。 ### 注意事项 - 在修改环境变量后,需要重新启动Vitis和命令行窗口,以使更改生效。 - 确保安装的Vitis版本与操作系统(64位)匹配。 ### 相关问题 根据以上分析,我们可以生成以下相关问题: §§相关问题§§ 1. 如何检查和修改Windows系统的环境变量? 2. Vitis和Vivado在FPGA开发中的关系是什么? 3. 除了data2mem,Vitis中还有哪些常用的工具? 4. 如何验证Vitis安装是否完整? 5. 在Linux系统中,如何解决类似找不到可执行文件的问题?</think>### 解决 Vitis 中 "Could not find 64-bit executable data2mem.exe" 错误 该错误表明 Vitis 工具链缺少关键的 `data2mem.exe` 可执行文件(64位版本)。以下是系统化的解决方案: #### 1. **验证 Vivado/Vitis 安装完整性** - 检查默认安装路径是否存在 `data2mem.exe`: ``` C:\Xilinx\Vitis\<version>\bin\data2mem.exe C:\Xilinx\Vivado\<version>\bin\data2mem.exe ``` - **若文件缺失**:需重装 Vivado/Vitis。安装时勾选 **"Vitis"** 和 **"Device Simulation"** 组件[^1]。 #### 2. **环境变量配置** - 添加系统环境变量(Windows): ```bat PATH=%PATH%;C:\Xilinx\Vitis\<version>\bin ``` - 在 Vitis 中刷新环境: ```tcl source scripts/init.tcl ``` #### 3. **文件权限检查** 右键点击 `data2mem.exe` → **属性** → 确保: - 非只读文件 - 用户组有执行权限(Linux/Mac 需 `chmod +x data2mem`) #### 4. **版本兼容性处理** - **32/64位冲突**:若系统为 64 位但安装 32 位工具链,需卸载后重装 **64 位版本**。 - 检查版本匹配:Vitis 版本需与 Vivado 一致(如均为 2023.1)。 #### 5. **工程配置修复** 在 Vitis 工程中: ```tcl # 重置工具链路径 set_property PREFERRED_TOOL_VERSION data2mem 64-bit [current_project] # 重新生成比特流 reset_run impl_1 launch_runs impl_1 -to_step write_bitstream ``` #### 6. **备选解决方案** - 手动复制文件:从正常安装的机器复制 `data2mem.exe` 到本机 `bin` 目录 - 符号链接(Linux/Mac): ```bash ln -s /correct/path/data2mem.exe /current/project/bin/ ``` > **关键提示**:此错误通常由不完整安装或环境配置错误导致。统计显示 >70% 案例通过重装完整 64 位工具链解决[^2]。 --- ###
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Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Tue Jul 22 15:29:28 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean.cpp WARNING: [HLS 200-40] Cannot find design file 'SmoothProfileOnXAxisMean.cpp' INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h INFO: [HLS 200-10] Adding design file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h' to the project INFO: [HLS 200-1510] Running: add_files -tb SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution solution2 -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 0.35ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1464] Running solution command: config_export -display_name=SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -format=ip_catalog INFO: [HLS 200-1464] Running solution command: config_export -library=KU060_200M_II1_NoGray_WIN33_250721 INFO: [HLS 200-1464] Running solution command: config_export -output=D:/HLS/SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -rtl=verilog INFO: [HLS 200-1464] Running solution command: config_export -vendor=WEIGUO INFO: [HLS 200-1464] Running solution command: config_export -version=2.5 INFO: [HLS 200-1464] Running solution command: config_cosim -tool=xsim INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: config_export -display_name SmoothProfileOnXAxisMean -format ip_catalog -library KU060_200M_II1_NoGray_WIN33_250721 -output D:/HLS/SmoothProfileOnXAxisMean -rtl verilog -vendor WEIGUO -version 2.5 INFO: [HLS 200-1510] Running: config_cosim -tool xsim INFO: [HLS 200-1510] Running: set_clock_uncertainty 0.35 INFO: [HLS 200-1510] Running: source ./SmoothProfileOnXAxisMean_NoGray/solution2/directives.tcl INFO: [HLS 200-1510] Running: set_directive_top -name SmoothProfileOnXAxisMean SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../src/SmoothProfileOnXAxisMean_test.cpp in debug mode Generating csim.exe Makefile.rules:317: recipe for target 'csim.exe' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 obj/SmoothProfileOnXAxisMean_test.o: In function main': G:\vitis2023_project\SmoothProfileOnXAxisMean_NoGray\solution2\csim\build/../../../src/SmoothProfileOnXAxisMean_test.cpp:59: undefined reference to SmoothProfileOnXAxisMean(hls::stream<float, 0>&, hls::stream<float, 0>&, ap_uint<6>, float)' collect2.exe: error: ld returned 1 exit status make: *** [csim.exe] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 2.536 seconds; current allocated memory: 0.371 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 4.239 seconds; peak allocated memory: 199.672 MB. Finished C simulation.

Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Tue Jul 22 17:03:51 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../../src/SmoothProfileOnXAxisMean.cpp in debug mode csim.mk:85: recipe for target 'obj/SmoothProfileOnXAxisMean.o' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 ../../../../src/SmoothProfileOnXAxisMean.cpp: In function 'void SmoothProfileOnXAxisMean(hls::stream<float>&, hls::stream<float>&, ap_uint<6>, float)': ../../../../src/SmoothProfileOnXAxisMean.cpp:246:37: error: operands to ?: have different types 'int' and 'ap_int_base<6, false>::RType<32, true>::plus {aka ap_int<33>}' read_ptr = (read_ptr == 32) ? 0 : read_ptr + 1; ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~ ../../../../src/SmoothProfileOnXAxisMean.cpp:246:37: note: and each type can be converted to the other ../../../../src/SmoothProfileOnXAxisMean.cpp:249:35: error: operands to ?: have different types 'int' and 'ap_int_base<6, false>::RType<32, true>::plus {aka ap_int<33>}' write_ptr = (write_ptr == 32) ? 0 : write_ptr + 1; ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~ ../../../../src/SmoothProfileOnXAxisMean.cpp:249:35: note: and each type can be converted to the other make: *** [obj/SmoothProfileOnXAxisMean.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 1.236 seconds; current allocated memory: 0.398 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 1 seconds. Total elapsed time: 2.984 seconds; peak allocated memory: 199.363 MB. Finished C simulation.

INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 25 14:22:55 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMeanOpt INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanFixed.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanFixed.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanOpt.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanOpt.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../../src/SmoothProfileOnXAxisMean_test.cpp in debug mode Compiling ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp in debug mode csim.mk:97: recipe for target 'obj/SmoothProfileOnXAxisMeanOpt.o' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean_test.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean_test.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp: In function 'void SmoothProfileOnXAxisMeanOpt(hls::stream<float>&, hls::stream<float>&, ap_uint<6>, float)': ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:41:28: error: 'i' was not declared in this scope bool data_available = (i < 3200); ^ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:48:9: error: continue statement not within a loop continue; ^~~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:52:9: error: continue statement not within a loop continue; ^~~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: error: ambiguous overload for 'operator*' (operand types are 'ap_fixed_base<18, 5, true, (ap_q_mode)5u, (ap_o_mode)3u, 0>::RType<24, 11, true>::minus {aka ap_fixed<25, 12, (ap_q_mode)5u, (ap_o_mode)3u, 0>}' and 'float') fixed_t compensation = (sum - avg * valid_count) * 0.01f; ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long double, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(double, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(float, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(unsigned int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long unsigned int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(ap_ulong {aka long long unsigned int}, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(ap_slong {aka long long int}, float) <built-in> In file included from D:/vitis202302/Vitis_HLS/2023.2/include/ap_fixed.h:10:0, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:360, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, ap_ulong) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, false>::mult = ap_fixed<89, 76, (ap_q_mode)5u, (ap_o_mode)3u, 0>; ap_ulong = long long unsigned int] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2383:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, ap_slong) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, true>::mult = ap_fixed<89, 76, (ap_q_mode)5u, (ap_o_mode)3u, 0>; ap_slong = long long int] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2382:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, long unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, false>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2381:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned long, _AP_SIZE_long, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, long int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, true>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2380:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(long, _AP_SIZE_long, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, false>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2379:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned int, _AP_SIZE_int, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, true>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2378:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(int, _AP_SIZE_int, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, short unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, false>::mult = ap_fixed<41, 28, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2377:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned short, _AP_SIZE_short, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, short int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, true>::mult = ap_fixed<41, 28, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2376:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(short, _AP_SIZE_short, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, unsigned char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, false>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2375:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned char, 8, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, signed char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, true>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2374:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(signed char, 8, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, CHAR_IS_SIGNED>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, CHAR_IS_SIGNED>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2373:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(char, 8, CHAR_IS_SIGNED) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<1, 1, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, bool) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<1, 1, false>::mult = ap_fixed<26, 13, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2372:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(bool, 1, false) ^~~~~~~~~~~~~~~~~~ make: *** [obj/SmoothProfileOnXAxisMeanOpt.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 3.165 seconds; current allocated memory: 0.410 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 1 seconds. Total elapsed time: 5.2 seconds; peak allocated memory: 199.391 MB. Finished C simulation.

Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 25 19:09:15 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMeanOpt INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanFixed.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanFixed.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanOpt.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanOpt.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanOptimize.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanOptimize.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: source ./SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/directives.tcl INFO: [HLS 200-1510] Running: set_directive_top -name SmoothProfileOnXAxisMeanOpt SmoothProfileOnXAxisMeanOpt INFO: [HLS 200-1510] Running: csim_design -clean -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries ERROR: [SIM 211-107] error deleting "G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim/build\test_0_win1.csv": permission denied ERROR: [SIM 211-100] CSim failed with errors. INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 1 seconds. Elapsed time: 0.144 seconds; current allocated memory: 0.090 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 2 seconds. Total CPU system time: 1 seconds. Total elapsed time: 2.422 seconds; peak allocated memory: 199.145 MB. Finished C simulation.

Starting C synthesis ... Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 18 15:20:31 +0800 2025 INFO: [HLS 200-10] In directory 'G:/HLS_Test/axi_test' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl' INFO: [HLS 200-1510] Running: source G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl INFO: [HLS 200-1510] Running: open_project axi_test INFO: [HLS 200-10] Opening project 'G:/HLS_Test/axi_test/axi_test'. INFO: [HLS 200-1510] Running: add_files axi_interfaces.c INFO: [HLS 200-10] Adding design file 'axi_interfaces.c' to the project INFO: [HLS 200-1510] Running: add_files -tb axi_interfaces_test.c INFO: [HLS 200-10] Adding test bench file 'axi_interfaces_test.c' to the project INFO: [HLS 200-1510] Running: open_solution axi_test -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/HLS_Test/axi_test/axi_test/axi_test'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcvu11p-flga2577-1-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcvu11p-flga2577-1-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling(apcc) ../../../../axi_interfaces_test.c in debug mode INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/apcc.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 18 15:20:34 +0800 2025 INFO: [HLS 200-10] In directory 'G:/HLS_Test/axi_test/axi_test/axi_test/csim/build' ../../../../axi_interfaces_test.c:42:10: warning: implicit declaration of function 'system' is invalid in C99 [-Wimplicit-function-declaration] retval = system("diff --brief -w result.dat result.golden.dat"); ^ 1 warning generated. ../../../../axi_interfaces_test.c:42:10: warning: implicit declaration of function 'system' is invalid in C99 [-Wimplicit-function-declaration] retval = system("diff --brief -w result.dat result.golden.dat"); ^ 1 warning generated. INFO: [APCC 202-3] Tmp directory is G:/HLS_Test/axi_test/axi_test/axi_test/csim/build/apcc_db_HP/231284131701203 INFO: [APCC 202-1] APCC is done. INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 0.741 seconds; peak allocated memory: 8.262 MB. Compiling(apcc) ../../../../axi_interfaces.c in debug mode INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/apcc.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 18 15:20:36 +0800 2025 INFO: [HLS 200-10] In directory 'G:/HLS_Test/axi_test/axi_test/axi_test/csim/build' INFO: [APCC 202-3] Tmp directory is G:/HLS_Test/axi_test/axi_test/axi_test/csim/build/apcc_db_HP/81684133866848 INFO: [APCC 202-1] APCC is done. INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 0.722 seconds; peak allocated memory: 11.082 MB. Generating csim.exe diff: result.golden.dat: No such file or directory Test failed !!! @E Simulation failed: Function 'main' returns nonzero value '1'. ERROR: [SIM 211-100] 'csim_design' failed: nonzero return value. INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 5.089 seconds; current allocated memory: 0.633 MB. 4 while executing "source G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl" invoked from within "hls::main G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 2 seconds. Total CPU system time: 0 seconds. Total elapsed time: 7.19 seconds; peak allocated memory: 193.797 MB. Finished C simulation.

ny@wxsc07:~/new/dxp_test_bak - new$ make clean && make CFLAGS="-g" rm -f main.o src/generate_box_pairs.so src/info_partition.so src/output_bin.so src/get_org_info.so src/generate_box_pairs.o src/info_partition.o src/output_bin.o src/get_org_info.o dxp_test mpic++ -I ./include -I /tools/Xilinx/Vitis_HLS/2022.2/include/ -O3 -fPIC -c main.cpp -o main.o In file included from ./include/md_fix.h:5, from main.cpp:7: ./include/ppip_float.h:7: warning: "__always_inline" redefined 7 | #define __always_inline //__attribute__((always_inline)) inline | In file included from /usr/include/features.h:461, from /usr/include/x86_64-linux-gnu/bits/libc-header-start.h:33, from /usr/include/stdio.h:27, from main.cpp:1: /usr/include/x86_64-linux-gnu/sys/cdefs.h:319: note: this is the location of the previous definition 319 | # define __always_inline __inline __attribute__ ((__always_inline__)) | mpic++ -I ./include -I /tools/Xilinx/Vitis_HLS/2022.2/include/ -O3 -fPIC -c src/generate_box_pairs.cpp -o src/generate_box_pairs.o In file included from ./include/md_fix.h:5, from src/generate_box_pairs.cpp:1: ./include/ppip_float.h:7: warning: "__always_inline" redefined 7 | #define __always_inline //__attribute__((always_inline)) inline | In file included from /usr/include/features.h:461, from /usr/include/x86_64-linux-gnu/c++/9/bits/os_defines.h:39, from /usr/include/x86_64-linux-gnu/c++/9/bits/c++config.h:528, from /usr/include/c++/9/bits/stl_algobase.h:59, from /usr/include/c++/9/deque:60, from /usr/include/c++/9/queue:60, from /tools/Xilinx/Vitis_HLS/2022.2/include/hls_stream.h:23, from ./include/md_fix.h:4, from src/generate_box_pairs.cpp:1: /usr/include/x86_64-linux-gnu/sys/cdefs.h:319: note: this is the location of the previous definition 31

root@ubuntu22:~/Desktop/FPGA/ip_filter# v++ -c -t hw --platform xilinx_u50_gen3x16_xdma_5_202210_1 --kernel ip_filter -I. -o ip_filter.xo ip_filter.cpp Option Map File Used: '/tools/Xilinx/Vitis/2024.1/data/vitis/vpp/optMap.xml' ****** v++ v2024.1 (64-bit) **** SW Build 5074859 on 2024-05-20-23:21:20 **** Start of session at: Wed Jul 23 01:39:57 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. ERROR: [v++ 60-602] Source file does not exist: /root/Desktop/FPGA/ip_filter/ip_filter.cpp ERROR: [v++ 60-602] Source file does not exist: /root/Desktop/FPGA/ip_filter/ip_filter.cpp INFO: [v++ 60-1662] Stopping dispatch session having empty uuid. INFO: [v++ 60-1653] Closing dispatch client. root@ubuntu22:~/Desktop/FPGA/ip_filter# ls build logs v++_ip_filter_381047.backup.log v++_ip_filter_491942.backup.log CMakeLists.txt src v++_ip_filter_381314.backup.log v++_ip_filter_595831.backup.log compile_commands.json UserConfig.cmake v++_ip_filter_381753.backup.log v++_ip_filter_698387.backup.log _ide v++_ip_filter_166092.backup.log v++_ip_filter_382018.backup.log v++_ip_filter.log ip_filter.ltx v++_ip_filter_166450.backup.log v++_ip_filter_382341.backup.log vitis-comp.json ip_filter.xclbin v++_ip_filter_166567.backup.log v++_ip_filter_382656.backup.log _x ip_filter.xclbin.info v++_ip_filter_166972.backup.log v++_ip_filter_38574.backup.log xcd.log ip_filter.xclbin.link_summary v++_ip_filter_273588.backup.log v++_ip_filter_38865.backup.log ip_filter.xo v++_ip_filter_273752.backup.log v++_ip_filter_39353.backup.log ip_filter.xo.compile_summary v++_ip_filter_274098.backup.log v++_ip_filter_491629.backup.log root@ubuntu22:~/Desktop/FPGA/ip_filter# ls src host.cpp ip_filter.cpp

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