IEEE Std 1800.2-2020：UVM通用验证方法学最新标准

PDF文件

下载需积分: 0 | 3.9MB | 更新于2024-06-26 | 162 浏览量 | 举报 1 收藏

立即下载

"uvm1800.2-2020是IEEE针对通用验证方法学（Universal Verification Methodology, UVM）发布的最新标准协议，该标准由IEEE计算机学会的设计自动化标准委员会制定。IEEE Std 1800.2-2020是2017版的修订版，主要涉及系统级集成电路（SOC）和IC验证中的验证方法学。这个标准参考手册旨在提升验证组件之间的互操作性，降低新项目中使用知识产权（IP）的成本。" 《IEEE Std 1800.2-2020：通用验证方法学语言参考手册》是设计自动化领域的关键规范，它定义了一套标准的、可复用的验证组件和框架，用于系统级集成电路和集成电路的设计验证。该标准建立在SystemVerilog语言之上，是Accellera Systems Initiative的UVM预IEEE类参考的进一步发展。 UVM的核心理念是提供一个可扩展的、基于组件的验证环境，这些组件可以被复用、组合和定制，以适应各种复杂的验证需求。它包含了一系列预先构建的类库，如代理（agent）、序列器（sequencer）、监控器（monitor）、断言（assertion）以及测试平台（testbench）等，这些都遵循一致的接口和通信协议，从而简化了验证环境的搭建和维护。 1. **组件模型**：UVM引入了一种组件化的方法来组织验证环境，每个组件都有明确的角色和职责，如代理负责与设计进行交互，序列器控制激励的生成，监控器观察设计行为，而环境则将这些组件协调起来。 2. **消息传递机制**：UVM使用事件和队列来实现组件间的通信，如`uvm_analysis_port`和`uvm.seq_item_port`用于数据传输，确保了验证信息的有序流动。 3. **配置和覆盖管理**：UVM提供了一套完整的配置和覆盖管理系统，允许用户在不修改组件源代码的情况下动态配置验证环境，以及收集和分析覆盖率数据。 4. **工厂和注册表**：UVM工厂负责创建组件实例，而注册表则使得组件可以被动态查找和实例化，增强了代码的可重用性和可扩展性。 5. **过程宏和便利函数**：UVM提供了一系列过程宏和便利函数，如`run_test`和`uvm_report`，简化了测试的启动和信息报告。 6. **断言和约束随机化**：UVM集成了SystemVerilog的断言和约束随机化功能，使得设计的行为可以被严格检查，同时激励的生成更加智能和可控。 7. **可扩展性**：UVM的架构允许用户自定义组件和扩展框架，以适应特定的验证需求，比如增加新的验证机制或优化性能。通过采用UVM标准，设计团队可以更有效地进行验证工作，减少重复劳动，提高验证质量和效率。此外，由于UVM的广泛采用，工程师们可以更容易地在不同的项目和团队之间共享知识和经验，促进了整个行业的标准化和进步。

IEEE Std 1800.2-2020

IEEE Standard for Universal Verification Methodology Language Reference Manual

2. Normative references

The following referenced documents are indispensable for the application of this document (i.e., they must be

understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of the

referenced document (including any amendments or corrigenda) applies.

IEEE Std 1800™, IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and

Verification Language.

4, 5

3. Definitions, acronyms, and abbreviations

For the purposes of this document, the following terms and definitions apply. The IEEE Standards Dictionary

Online should be consulted for terms not defined in this clause.

3.1 Definitions

agent: An abstract container used to emulate and verify device under test (DUT) devices; agents encapsulate a

driver, sequencer, and monitor.

blocking: An interface where tasks block execution until they complete. See also: non-blocking.

component: A piece of verification intellectual property (VIP) that provides functionality and interfaces.

consumer: A verification component that receives transactions from another component.

driver: A component responsible for executing or otherwise processing transactions, usually interacting with

the device under test (DUT) to do so.

environment: The container object that defines the testbench topology.

export: A transaction-level modeling (TLM) interface that provides an implementation of methods used for

communication. Used in Universal Verification Methodology (UVM) to connect to a port.

factory method: A classic software design pattern used to create generic code by deferring, until run time, the

exact specification of the object to be created.

hook: A method that enables users to customize certain behaviors of a component.

generator: A verification component that provides transactions to another component. Also referred to as a

producer.

monitor: A passive entity that samples device under test (DUT) signals, but does not drive them.

non-blocking: A call that returns immediately. See also: blocking.

policy: A collection of settings used to apply an operation to a class.

port: A transaction-level modeling (TLM) interface that defines the set of methods used for communication.

Used in Universal Verification Methodology (UVM) to connect to an export.

proxy: A class functioning as an interface to another component or class.

request: A transaction that provides information to initiate the processing of a particular operation.

response: A transaction that provides information about the completion or status of a particular operation.

IEEE publications are available from the Institute of Electrical and Electronics Engineers (http://standards.ieee.org/).

The IEEE standards or products referred to in Clause 2 are trademarks owned by the Institute of Electrical and Electronics Engineers,

Incorporated.

IEEE Standards Dictionary Online is available at: http://ieeexplore.ieee.org/.

Authorized licensed use limited to: University of Canberra. Downloaded on October 03,2020 at 14:34:46 UTC from IEEE Xplore. Restrictions apply.

IEEE Std 1800.2-2020

IEEE Standard for Universal Verification Methodology Language Reference Manual

scoreboard: The mechanism used to dynamically predict the response of the design and check the observed

response against the predicted response. Usually, refers to the entire dynamic response-checking structure.

sequence: A Universal Verification Methodology (UVM) object that procedurally defines a set of transactions

to be executed and/or controls the execution of other sequences.

sequencer: An advanced stimulus generator that executes sequences that define the transactions provided to

the driver for execution.

singleton: A design pattern where the creation of the class only has one instance of that class.

test: Specific customization of an environment to exercise required functionality of the device under test

(DUT).

testbench: The structural definition of a set of verification components used to verify a device under test

(DUT). Also referred to as a verification environment.

transaction: A class instance that encapsulates information used to communicate between two or more

components.

user: Someone that uses the Universal Verification Methodology (UVM) base class library (BCL).

NOTE—In this standard, user uses the classes, functions, methods, or macros defined herein.

3.2 Acronyms and abbreviations

API application programming interface

BCL base class library

DPI direct programming interface

DUT device under test

EDA electronic design automation

FIFO first-in, first-out

HDL hardware description language

IP intellectual property

RTL register transfer level

TLM transaction-level modeling

UVM Universal Verification Methodology

VIP verification intellectual property

Notes in text, tables, and figures are given for information only and do not contain requirements needed to implement the standard.

Authorized licensed use limited to: University of Canberra. Downloaded on October 03,2020 at 14:34:46 UTC from IEEE Xplore. Restrictions apply.

IEEE Std 1800.2-2020

IEEE Standard for Universal Verification Methodology Language Reference Manual

4. Universal Verification Methodology (UVM) class reference

The UVM base class library provides the building blocks needed to quickly develop well-constructed and

reusable verification components and test environments in SystemVerilog. All UVM application programming

interface (API) should maintain random stability.

The UVM classes and utilities are divided into the following categories pertaining to their role or function. The

subsequent clauses of this standard give a more detailed overview of each category—and the classes that

comprise them.

Base—The basic building blocks for all environments are components, which do the actual work, transactions,

which convey information between components, and ports, which provide the interfaces used to convey

transactions. The UVM’s core base classes provide these building blocks. See Clause 5.

Reporting—The reporting classes provide a facility for issuing reports (messages) with consistent formatting

and configurable side effects, such as logging to a file or exiting simulation. Reports can also filter out

messages based on their verbosity, unique ID, or severity. See Clause 6.

Recording—The recording classes provide a facility to record transactions into a database using a consistent

API. Users can configure what gets sent to the back-end database without knowing exactly how the connection

to that database is established. See Clause 7.

Factory—As the name implies, the UVM factory is used to manufacture (create) UVM objects and

components. A factory can be configured to produce an object of a given type on a global or instance basis.

Factories allow dynamically configurable component hierarchies and object substitutions without having to

modify their code or break encapsulation. See Clause 8.

Phasing—This category defines the phasing capability provided by UVM. See Clause 9.

Synchronization—These event and barrier synchronization classes can be used for process synchronization. See

Clause 10.

Containers—These classes are type parameterized data structures that provide queue and pool services. The

class-based queue and pool types allow for efficient sharing of the data structures compared with their

SystemVerilog built-in counterparts. See Clause 11.

UVM TLM—The UVM transaction-level modeling (TLM) library defines several abstract, transaction-level

interfaces, and the ports and exports that facilitate their use. Each UVM TLM interface consists of one or more

methods used to transport data, typically whole transactions (objects) at a time. Component designs that use

UVM TLM ports and exports to communicate are inherently more reusable, interoperable, and modular. See

Clause 12.

Components—Components form the foundation of UVM. They encapsulate the behavior of drivers,

scoreboards, and other objects in a testbench. The UVM base class library provides a set of predefined

component types, all derived directly or indirectly from uvm_component. See Clause 13.

Sequences—Sequences encapsulate user-defined procedures that generate multiple uvm_sequence_item–based

transactions (see 14.1). Such sequences can be reused, extended, randomized, and combined sequentially and

hierarchically in interesting ways to produce realistic stimulus to a device under test (DUT). See Clause 14.

Sequencers—The sequencer serves as an arbiter for controlling transaction flow from multiple stimulus

generators. More specifically, the sequencer controls the flow of uvm_sequence_item–based transactions (see

14.1) generated by one or more uvm_sequence #(REQ,RSP)–based sequences (see 14.3). See Clause 15.

Authorized licensed use limited to: University of Canberra. Downloaded on October 03,2020 at 14:34:46 UTC from IEEE Xplore. Restrictions apply.

IEEE Std 1800.2-2020

IEEE Standard for Universal Verification Methodology Language Reference Manual

Policies—Each of UVM’s policy classes performs a specific task for uvm_object–based objects: printing,

comparing, recording, packing, and unpacking (see 5.3). They are implemented separately from uvm_object to

allow for different ways to print, compare, etc., without modifying the object class being utilized; e.g., a user

can simply apply a different printer or compare policy to change how an object is printed or compared. See

Clause 16.

registers and memories in a design under test (DUT)

. See Clause 17.

Macros—UVM provides several macros to help increase user productivity. See Annex B.

Configuration and resources—These classes provide a configuration database, which is used to store and

retrieve both configuration time and run-time properties. See Annex C.

Package scope—This category defines a small list of types, variables, functions, and tasks defined in the

uvm_pkg scope. These items are accessible from any scope that imports the uvm_pkg. See Annex F.

Command line processor—This a general interface to the command line arguments that were provided for the

given simulation. See Annex G.

5. Base classes

5.1 Overview

The UVM base class library defines a set of base classes and utilities that facilitate the design of modular,

scalable, and reusable verification environments. The basic building blocks for all environments are

components and the transactions they use to communicate.

a) uvm_object—All components and transactions derive from uvm_object (see 5.3), which defines an

interface of core class-based operations: create, copy, compare, print, sprint, record, etc. It also defines

interfaces for instance identification (name, type name, unique id, etc.) and random seeding. All

derivatives of uvm_object are factory enabled, unless otherwise specified.

b) uvm_component—The uvm_component class (see 13.1) is the base class for all UVM components.

Components are quasi-static objects that exist throughout simulation. This allows them to establish

structural hierarchy much like modules and program blocks. Components participate in a phased test

flow during the course of simulation. Each phase—build, connect, run, etc.—is defined by a callback

that is executed in precise order. Finally, the uvm_component also defines any configuration,

reporting, transaction recording, and factory interfaces.

c) uvm_transaction—The uvm_transaction (see 5.4) is the root base class for UVM transactions,

which, unlike uvm_components (see 13.1), are transient in nature. It extends uvm_object (see 5.3) to

include a timing and recording interface. Simple transactions can derive directly from

uvm_transaction, while sequence-enabled transactions derive from uvm_sequence_item (see 14.1).

5.2 uvm_void

The uvm_void class is the abstract base class for all UVM classes. It is an abstract class with no data members

or functions. It allows for creation of generic containers of objects, similar to a void pointer in the C

programming language. User classes derived directly from uvm_void inherit none of the UVM functionality,

but such classes may be placed in uvm_void-typed containers along with other UVM objects.

Authorized licensed use limited to: University of Canberra. Downloaded on October 03,2020 at 14:34:46 UTC from IEEE Xplore. Restrictions apply.

剩余457页未读，继续阅读

qyxu

粉丝: 3

IEEE Std 1800.2-2020：UVM通用验证方法学最新标准

UVM-18002-2020-10tar.gz

1800.2-2017.zip_1800_1800.2_IEEE UVM_ieee 1800 2017_ieee 1800.2-

IEEE 1800.2-2020 UVM标准修订详解

SV IEEE 1800-2017 and UVM IEEE 1800.2-2017.rar

最新的SV IEEE 1800-2017 和 UVM IEEE 1800.2-2017英文版

IEEE Std 1800.2-2020 通用验证方法学语言参考说明 - 完整英文电子版（458页）.zip

2020年UVM验证方法论标准详解：IEEE Std 1800.2-2020

IEEE 1800.2-2020标准：UVM通用验证方法论参考手册

探索IEEE Std 1800.2-2020通用验证方法学电子版

系统级验证权威指南：SV IEEE 1800-2017与UVM IEEE 1800.2-2017

最新资源