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MQ常见问题解决与排查技巧

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在本文档中,我们收集并整理了关于MQ(Message Queue,消息队列)常见问题的解答,以便于IT专业人士解决实际工作中可能遇到的挑战。以下是一些关键知识点: 1. **通道连通性检测**:确定发送通道与接收方服务器是否连通的方法是使用MQ发送方通道的PING功能。如果操作成功,会得到响应;如果失败,则表明连接存在问题。 2. **错误日志查看**: - Windows用户可以通过事件查看器控制面板中的管理工具-事件查看器来查看MQ的错误日志。 - 对于特定错误代码(如20352059),可以在DOS命令台使用MQRCAMQ[IDNUM]进行查询。 3. **消息发送确认**:确认消息是否全部发送出去,需查看传输队列的消息列表,确保队列属性允许查看消息。 4. **接收问题诊断**: - 检查接收端是否开启,特别是确认消息接收端是否设置了接收未发出的消息。 - 检查本地队列和死信队列,死信队列中的消息可能需要与对方管理员确认配置。 5. **通道和接收端状态**: - 确认接收端通道是否正常工作,以及其是否处于活动状态。 - 如果接收端处于非活动状态,尝试启动并检查启动结果。 6. **日志分析**:对于任何异常错误信息,都需要仔细检查MQ的日志文件,通常位于安装目录下的`qmgrs/MQ0000/errors`文件夹。 7. **跨服务器通信问题**:如果消息无法正常发送或接收,应首先排查本地问题,并在必要时请求对方MQ管理员协助,查看发送方通道的状态。 8. **消息发送与接收验证**:为了确认消息是否成功从发送方MQ服务器发送到接收方,需要检查发送方通道的状态以及查看相关日志。 这些知识点涵盖了MQ日常运维中常见的问题排查和解决策略,有助于IT人员快速定位和解决MQ系统中的问题,提高工作效率。

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void defult_output(uint8_t ID) // { uint32_t freq_s=0; uint32_t freq_e=0; uint32_t freq_s1=0; uint32_t freq_e1=0; SHDN2_ON; PA_OFF; Attenuator_control(0); Read_Flash(WRITE_FRQ2_ADDR,frq_change_data2,42); Read_Flash(WRITE_TEMP2_ADDR,Cali_Temp,1); //读取标校时的温度数据 if(ID==0) { // SHDN1_ON; // Read_Flash(WRITE_FRQ1_ADDR,frq_change_data,42); //读取FALSH中的标校数据 // // freq_s=Get_Calibration_Frq(700,Temp,Cali_Temp[0]);//P段重点频段880Mhz中心频点,100M带宽,补偿0.6起始频率为770Mhz,进行温度补偿 // freq_e=Get_Calibration_Frq(1060,Temp,Cali_Temp[0]);//P段重点频段880Mhz中心频点,100M带宽,补偿0.3终止频率为960Mhz,进行温度补偿 // defult_start = Get_frq_change_V(frq_change_data2,Voltage_Data,freq_s,VOLTAGE_NUMBER,256,ID,2); // defult_end = Get_frq_change_V(frq_change_data2,Voltage_Data,freq_e,VOLTAGE_NUMBER,256,ID,2); // DAC_control(defult_start,defult_end,DA_Write_Date2,50,DAC_OUTPUT_POINT,2); freq_s1=Get_Calibration_Frq(410,Temp,Cali_Temp[0]);//P段重点频段433Mhz中心频点,20M带宽,补偿0.6起始频率为411Mhz,进行温度补偿 freq_e1=Get_Calibration_Frq(480,Temp,Cali_Temp[0]);//P段重点频段433Mhz中心频点,20M带宽,补偿0.3终止频率为449Mhz,进行温度补偿 defult_start1 = Get_frq_change_V(frq_change_data2,Voltage_Data,freq_s,VOLTAGE_NUMBER,256,ID,1); defult_end1 = Get_frq_change_V(frq_change_data2,Voltage_Data,freq_e,VOLTAGE_NUMBER,256,ID,1); DAC_control(defult_start1,defult_end1,DA_Write_Date,50,DAC_OUTPUT_POINT,1); }这段代码什么意思

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case (fsm_Cmd_ctrl) //-------------------------------------------------------------------------------------------------------------- // State-0, 上电初始化操控源选择 FSM_CmdCtrl_SEL_INIT_SRC: begin //fsm_Cmd_ctrl <= #1 (SW_HOST_INIT_MIPI_ON)? FSM_CmdCtrl_HOST_INIT : FSM_CmdCtrl_MCU_INIT; fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_MCU_INIT; end //-------------------------------------------------------------------------------------------------------------- // State-1, MCU上电初始化配置2828和Command操作 FSM_CmdCtrl_MCU_INIT: begin // 进行MCU配置 (在启动fpga操作使能之前) if (mcuCfg_fpga_ena == 0) begin // 寄存器0xd8h fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_MCU_INIT; // MCU对ssd2828和fpga Cmd_if共同设置 case(MIPI_COMMAND_VIDEO_MOD_SEL) // 0: 正常工作时, 由上层MCU或FPGA host选择模式 0: mipi_mod_sel <= #1 mcuCfg_mipi_mod_sel ; // (寄存器0xd0h bit0) // 1: 在调试时, 强制设为Video模式 1: mipi_mod_sel <= #1 0 ; // 2: 在调试时, 强制设为Command模式 2: mipi_mod_sel <= #1 1 ; default: mipi_mod_sel <= #1 mcuCfg_mipi_mod_sel ; endcase // MCU设置2828 mipi_Cmd_if_bus_type <= #1 mcuCfg_mipi_Cmd_if_bus_type ; // 寄存器0x50h bit1 // MCU设置fpga Cmd数据方式 Cmd_dat_tx_mod <= #1 mcuCfg_Cmd_dat_tx_mod ; // 寄存器0x65h bit2-0 // MCU读写2828操作 CmdIf_eclk_frq <= #1 mcuCfg_CmdIf_eclk_frq ; // 寄存器0x51h bit4-2 CmdIf_op_type <= #1 mcuCfg_CmdIf_op_type ; // 寄存器0x51h bit1-0 CmdIf_op_ena <= #1 mcuCfg_CmdIf_op_ena ; // 寄存器0x57h bit0 CmdIf_reg <= #1 mcuCfg_CmdIf_reg ; // 寄存器0x53h CmdIf_wr_dat[15:0] <= #1 mcuCfg_CmdIf_wr_param ; // 寄存器0x54/55h CmdIf_wr_dat[23:16] <= #1 0 ; CmdIf_wr_dat1[15:0] <= #1 mcuCfg_CmdIf_wr_param ; // 寄存器0x54/55h CmdIf_wr_dat1[23:16] <= #1 0 ; mcuCfg_CmdIf_rd_param_ch1 <= #1 w_CmdIf_rd_dat0[15:0] ; // 寄存器0x63/64h mcuCfg_CmdIf_rd_param_ch2 <= #1 w_CmdIf_rd_dat1[15:0] ; // 寄存器0x63/64h mcuCfg_CmdIf_rd_param_ch3 <= #1 w_CmdIf_rd_dat2[15:0] ; // 寄存器0x63/64h mcuCfg_CmdIf_rd_param_ch4 <= #1 w_CmdIf_rd_dat3[15:0] ; // 寄存器0x63/64h // MCU读取CmdIf工作状态 mcuCfg_CmdIf_op_state <= #1 w_CmdIf_op_state ; // 寄存器0x52h bit1-0 mcuCfg_CmdIf_op_finish <= #1 w_CmdIf_op_finish ; // 寄存器0x52h bit7 mcuCfg_CmdIf_rw_dat_count <= #1 w_CmdIf_rw_dat_count ; // 寄存器0x70~73h end // 配置完成后启动fpga操作使能 else begin // 当启动fpga操作使能后, MCU将不能重新配置 mipi_mod_sel <= #1 mipi_mod_sel ; mipi_Cmd_if_bus_type <= #1 mipi_Cmd_if_bus_type ; Cmd_dat_tx_mod <= #1 Cmd_dat_tx_mod ; CmdIf_eclk_frq <= #1 CmdIf_eclk_frq ; CmdIf_op_type <= #1 CmdIf_op_type ; CmdIf_op_ena <= #1 CmdIf_op_ena ; CmdIf_reg <= #1 CmdIf_reg ; CmdIf_wr_dat <= #1 CmdIf_wr_dat ; CmdIf_wr_dat1 <= #1 CmdIf_wr_dat1 ; //mcuCfg_CmdIf_rd_param <= #1 mcuCfg_CmdIf_rd_param ; mcuCfg_CmdIf_op_state <= #1 mcuCfg_CmdIf_op_state ; mcuCfg_CmdIf_op_finish <= #1 mcuCfg_CmdIf_op_finish ; mcuCfg_CmdIf_rw_dat_count <= #1 mcuCfg_CmdIf_rw_dat_count ; // 如果设置为Command模式, 将进入fpga发送rgb数据状态, Cmd_if模块动作 if (mipi_mod_sel == 1) begin fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_CMD_BUF_1st_ENA; end // 否则(为video模式), 本状态机将进入停止状态, 以及Cmd_if模块将不动作 else begin fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_STOP; end end end //-------------------------------------------------------------------------------------------------------------- // State-3, 在初始化后输入第一幅lvds rgb图到Cmd_buf中 FSM_CmdCtrl_CMD_BUF_1st_ENA: begin // 当host rgb ok时,进行缓存操作 if(host_rgb_ready) begin // 使能Cmd_buf_dat poc_host_Cmd_dat_ena <= #1 1; // 当首行数据缓存到fifo中时, 则确定发2828参数或数据操作 if (host_Cmd_dat_hs_wr_done_flag) begin fsm_Cmd_ctrl <= #1 (SW_TX_BMP_PARAM_WHEN_INIT_END == 1) ? FSM_CmdCtrl_NXT_BMP_DO_CFG : FSM_CmdCtrl_FPGA_TX_DAT; end end end //-------------------------------------------------------------------------------------------------------------- // State-4, lvds rgb数据发给2828 (2828在HS状态下发数据) // Cmd_buf 读写原理是: 先写完一行, 后读该行, 以避免pclk较小时导致无数据读 // 当读无效时, 表明该行数据全部读完, 则进入下一状态配置2828参数. FSM_CmdCtrl_FPGA_TX_DAT: begin // 确认2828数据位宽为24bit mipi_Cmd_if_bus_type <= #1 1; // 保持使能Cmd_buf_dat poc_host_Cmd_dat_ena <= #1 1; // 在每行参数发完后, 延迟发数据 if (cnt_hs_tx_dat_dly < HS_TX_DAT_DLY ) begin cnt_hs_tx_dat_dly <= #1 cnt_hs_tx_dat_dly + 1; fsm_Cmd_ctrl <= #1 fsm_Cmd_ctrl; cs_rst <= #1 cnt_hs_tx_dat_dly == 18; end else begin // 发数据状态机 case (fsm_Cmd_tx_dat_op) // Step-0, 当fifo读有效, 进入下一状态取出数据. (因fifo写完数据后会延迟输出rd dat) FSM_CmdDat_CHK_FIFO_VAVID: begin poc_host_Cmd_dat_rd_en <= #1 0; CmdIf_wr_dat <= #1 0; CmdIf_wr_dat1 <= #1 0; CmdIf_op_ena <= #1 0; CmdIf_op_turbo <= #1 0; // 设置操作为加速模式 wait_2828_op_cnt <= #1 0; fsm_Cmd_tx_dat_op <= #1 (r1_pic_host_Cmd_dat_rd_valid)? FSM_CmdDat_RD_FIFO : FSM_CmdDat_CHK_FIFO_VAVID; end // Step-1, 当fifo读有效, 则取出当前数据, 若读无效, 表示当前行数据读完, 则停止后续操作 FSM_CmdDat_RD_FIFO: begin // 设置写入2828 CmdIf_eclk_frq <= #1 3'b111; CmdIf_op_ena_buf <= #1 2'b10; CmdIf_op_turbo <= #1 1; // 设置操作为加速模式 // 当fifo读有效, 取出数据 if (r1_pic_host_Cmd_dat_rd_valid) begin if (cnt_rd_fifo_dat <= pid_hsd_true_pixel_dummy - 1)begin poc_host_Cmd_dat_rd_en <= #1 1; CmdIf_wr_dat <= #1 pid_host_Cmd_dat_out; CmdIf_wr_dat1 <= #1 pid_host_Cmd_dat_out1; CmdIf_op_type <= #1 2'b01; CmdIf_op_ena <= #1 1; cs_rst <= #1 0; fsm_Cmd_tx_dat_op <= #1 FSM_CmdDat_TX_DOING; // 计数读出个数 cnt_rd_fifo_dat <= #1 cnt_rd_fifo_dat + 1; // 是第一个数据则打开op切换标志 CmdIf_op_sw_flag <= #1 (cnt_rd_fifo_dat == 0)? 1 : 0; end // 否则表示行读完, 进入操作结束状态 else begin CmdIf_op_ena <= #1 1; CmdIf_op_type <= #1 2'b11; // 设置CmdIf模块END状态 poc_host_Cmd_dat_rd_en <= #1 0; CmdIf_wr_dat <= #1 0; CmdIf_wr_dat1 <= #1 0; cnt_rd_fifo_dat <= #1 0; fsm_Cmd_tx_dat_op <= #1 FSM_CmdDat_TX_DONE; end end end // Step-2, 将当前数据发给2828, 当完成后返回Step2, 重新读fifo FSM_CmdDat_TX_DOING: begin poc_host_Cmd_dat_rd_en <= #1 0 ; CmdIf_op_ena <= #1 1 ; CmdIf_op_ena_buf <= #1 CmdIf_op_ena_buf << 1 ; // 等待操作2828 //fsm_Cmd_tx_dat_op <= #1 ( CmdIf_op_finish_flag)? FSM_CmdDat_RD_FIFO : FSM_CmdDat_TX_DOING; fsm_Cmd_tx_dat_op <= #1 FSM_CmdDat_RD_FIFO ; //modify for speedup eclk end // Step-3, 当一行数据发给2828后停止写操作 FSM_CmdDat_TX_DONE: begin CmdIf_op_ena <= #1 1; // CmdIf模块进入END状态 fsm_Cmd_tx_dat_op <= #1 FSM_CmdDat_OP_END; poc_host_Cmd_dat_rd_en <= #1 0; CmdIf_wr_dat <= #1 0; CmdIf_wr_dat1 <= #1 0; wait_2828_op_cnt <= #1 0; CmdIf_op_type <= #1 2'b11; // 设置CmdIf模块END状态 cnt_rd_fifo_dat <= #1 0; end // Step-4, 操作结束, 返回控制状态机 FSM_CmdDat_OP_END: begin CmdIf_op_ena <= #1 0; CmdIf_op_turbo <= #1 0; cnt_hs_tx_dat_dly <= #1 0; fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_HS_DONE_CFG; fsm_Cmd_tx_dat_op <= #1 FSM_CmdDat_CHK_FIFO_VAVID; end default: begin fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_FPGA_TX_DAT; fsm_Cmd_tx_dat_op <= #1 FSM_CmdDat_CHK_FIFO_VAVID; CmdIf_op_ena <= #1 0; CmdIf_op_ena_buf <= #1 2'b10; poc_host_Cmd_dat_rd_en <= #1 0; CmdIf_wr_dat <= #1 0; CmdIf_wr_dat1 <= #1 0; wait_2828_op_cnt <= #1 0; cnt_hs_tx_dat_dly <= #1 0; end endcase end end //-------------------------------------------------------------------------------------------------------------- // State-5, 在当前行数据发完后, 相关操作和配置(2828) FSM_CmdCtrl_HS_DONE_CFG: begin // 若当前图像一帧或全部显示行发完后, 则进入帧完成操作状态 if (host_Cmd_dat_hs_disp_wr_done) begin poc_host_Cmd_dat_ena <= #1 0; fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_BMP_DONE_CFG; end // 否则进行当前行结束后的配置和操作 else begin // 保持Cmd_buf(fifo)继续缓存数据 poc_host_Cmd_dat_ena <= #1 1; // 延迟进行配置操作 //if (cnt_hs_tx_done_cfg_dly < HS_TX_DONE_CFG_DLY ) begin if (cnt_hs_tx_done_cfg_dly < 10 ) begin cnt_hs_tx_done_cfg_dly <= #1 cnt_hs_tx_done_cfg_dly + 1; fsm_Cmd_ctrl <= #1 fsm_Cmd_ctrl; end // 根据MCU或host配置的不同的mipi tx模式, 进行相应操作 else begin case (Cmd_dat_tx_mod) // 行tx模式 // (使host配置2828回LP状态) 'd0: begin // 提供host配置信息 poc_datu_dat_tx_type <= #1 0; // 2828行传输模式 poc_datu_param_type <= #1 3; // 每行传输后配置2828 // 提供host配置接口 CmdIf_eclk_frq <= #1 hostCfg_CmdIf_eclk_frq ; CmdIf_op_type <= #1 hostCfg_CmdIf_op_type ; CmdIf_op_ena <= #1 hostCfg_CmdIf_op_ena ; CmdIf_reg <= #1 hostCfg_CmdIf_reg ; CmdIf_wr_dat[15:0] <= #1 hostCfg_CmdIf_wr_param ; CmdIf_wr_dat[23:16] <= #1 0 ; CmdIf_wr_dat1[15:0] <= #1 hostCfg_CmdIf_wr_param ; CmdIf_wr_dat1[23:16] <= #1 0 ; poc_hostCfg_CmdIf_op_finish <= #1 w_CmdIf_op_finish ; // 2828数据位宽为24bit mipi_Cmd_if_bus_type <= #1 1 ; // 使能host配置 // 当host配置完成, 则本操作结束, 进入下一行配置状态 if (host_cfg_datu_param_done_flag) begin poc_host_cfg_datu_param_ena <= #1 0; cnt_hs_tx_done_cfg_dly <= #1 0; fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_WAIT_NXT_HS_BUF_DONE; end else begin poc_host_cfg_datu_param_ena <= #1 1; cnt_hs_tx_done_cfg_dly <= #1 cnt_hs_tx_done_cfg_dly; fsm_Cmd_ctrl <= #1 fsm_Cmd_ctrl; end end // 帧tx模式 // (目前无需配置2828) 'd1: begin poc_host_cfg_datu_param_ena <= #1 0; cnt_hs_tx_done_cfg_dly <= #1 0; fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_WAIT_NXT_HS_BUF_DONE; end endcase end end end //-------------------------------------------------------------------------------------------------------------- // State-6, 等待下一行数据缓存好后进行下一行相关操作和配置(2828) FSM_CmdCtrl_WAIT_NXT_HS_BUF_DONE: begin // 保持Cmd_buf(fifo)继续缓存数据 poc_host_Cmd_dat_ena <= #1 1; if (host_Cmd_dat_hs_wr_done_flag) begin fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_NXT_HS_DO_CFG; end end //-------------------------------------------------------------------------------------------------------------- // State-7, 在下一行数据发之前, 相关操作和配置(2828), 完成后重新进入数据发送状态 FSM_CmdCtrl_NXT_HS_DO_CFG: begin // 根据MCU或host配置的不同的mipi tx模式, 进行相应操作 case (Cmd_dat_tx_mod) // 行tx模式 // (使host配置2828回LP状态) 'd0: begin // 提供host配置信息 poc_datu_dat_tx_type <= #1 0; // 2828行传输模式 poc_datu_param_type <= #1 2; // 每行传输前配置2828 // 提供host配置接口 CmdIf_eclk_frq <= #1 hostCfg_CmdIf_eclk_frq ; CmdIf_op_type <= #1 hostCfg_CmdIf_op_type ; CmdIf_op_ena <= #1 hostCfg_CmdIf_op_ena ; CmdIf_reg <= #1 hostCfg_CmdIf_reg ; CmdIf_wr_dat[15:0] <= #1 hostCfg_CmdIf_wr_param ; CmdIf_wr_dat[23:16] <= #1 0 ; CmdIf_wr_dat1[15:0] <= #1 hostCfg_CmdIf_wr_param ; CmdIf_wr_dat1[23:16] <= #1 0 ; poc_hostCfg_CmdIf_op_finish <= #1 w_CmdIf_op_finish ; // 2828数据位宽为24bit mipi_Cmd_if_bus_type <= #1 1 ; // 使能host配置 // 当host配置完成, 则本操作结束, 返回数据发送状态 if (host_cfg_datu_param_done_flag) begin poc_host_cfg_datu_param_ena <= #1 0; //cnt_nxt_hs_tx_do_cfg_dly <= #1 0; fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_FPGA_TX_DAT; end else begin poc_host_cfg_datu_param_ena <= #1 1; //cnt_nxt_hs_tx_do_cfg_dly <= #1 cnt_nxt_hs_tx_do_cfg_dly; fsm_Cmd_ctrl <= #1 fsm_Cmd_ctrl; end end // 帧tx模式 // (目前无需配置2828, 保持数据发送状态) 'd1: begin poc_host_cfg_datu_param_ena <= #1 0; //cnt_nxt_hs_tx_do_cfg_dly <= #1 0; fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_FPGA_TX_DAT; end endcase end //-------------------------------------------------------------------------------------------------------------- // State-8, 在当前图片(一帧 或 所要显示的全部行)发完后, 相关操作和配置(2828) FSM_CmdCtrl_BMP_DONE_CFG: begin // 关闭Cmd_buf(fifo)缓存数据 poc_host_Cmd_dat_ena <= #1 0; // 延迟进行配置操作 if (cnt_vs_tx_done_cfg_dly < VS_TX_DONE_CFG_DLY ) begin cnt_vs_tx_done_cfg_dly <= #1 cnt_vs_tx_done_cfg_dly + 1; fsm_Cmd_ctrl <= #1 fsm_Cmd_ctrl; end // 根据MCU或host配置的不同的mipi tx模式, 进行相应操作 else begin case (Cmd_dat_tx_mod) // 行tx模式 // (使host配置2828回LP状态) 'd0, 'd1: begin // 提供host配置信息 poc_datu_dat_tx_type <= #1 0; // 2828行传输模式 poc_datu_param_type <= #1 3; // 每行传输后配置2828 // 提供host配置接口 CmdIf_eclk_frq <= #1 hostCfg_CmdIf_eclk_frq ; CmdIf_op_type <= #1 hostCfg_CmdIf_op_type ; CmdIf_op_ena <= #1 hostCfg_CmdIf_op_ena ; CmdIf_reg <= #1 hostCfg_CmdIf_reg ; CmdIf_wr_dat[15:0] <= #1 hostCfg_CmdIf_wr_param ; CmdIf_wr_dat[23:16] <= #1 0 ; CmdIf_wr_dat1[15:0] <= #1 hostCfg_CmdIf_wr_param ; CmdIf_wr_dat1[23:16] <= #1 0 ; poc_hostCfg_CmdIf_op_finish <= #1 w_CmdIf_op_finish ; // 2828数据位宽为24bit mipi_Cmd_if_bus_type <= #1 1 ; // 使能host配置 // 当host配置完成, 则本操作结束, 进入检测切图状态 if (host_cfg_datu_param_done_flag) begin poc_host_cfg_datu_param_ena <= #1 0; cnt_vs_tx_done_cfg_dly <= #1 0; fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_CHK_NXT_BMP; end else begin poc_host_cfg_datu_param_ena <= #1 1; cnt_vs_tx_done_cfg_dly <= #1 cnt_vs_tx_done_cfg_dly; fsm_Cmd_ctrl <= #1 fsm_Cmd_ctrl; end end endcase end end //-------------------------------------------------------------------------------------------------------------- // State-9, 检测是否有下一图片 (检测切图) FSM_CmdCtrl_CHK_NXT_BMP: begin // 保持关闭Cmd_buf(fifo)缓存数据 poc_host_Cmd_dat_ena <= #1 0; // 若有下一图片则进入帧/切图配置相关状态 if (host_qietu_done_flag) begin fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_WAIT_NXT_BMP_BUF_DONE; end else begin // MCU设置2828 mipi_Cmd_if_bus_type <= #1 mcuCfg_mipi_Cmd_if_bus_type ; // 寄存器0x50h bit1 // MCU设置fpga Cmd数据方式 Cmd_dat_tx_mod <= #1 mcuCfg_Cmd_dat_tx_mod ; // 寄存器0x65h bit2-0 // MCU读写2828操作 CmdIf_eclk_frq <= #1 mcuCfg_CmdIf_eclk_frq ; // 寄存器0x51h bit4-2 CmdIf_op_type <= #1 mcuCfg_CmdIf_op_type ; // 寄存器0x51h bit1-0 CmdIf_op_ena <= #1 mcuCfg_CmdIf_op_ena ; // 寄存器0x57h bit0 CmdIf_reg <= #1 mcuCfg_CmdIf_reg ; // 寄存器0x53h CmdIf_wr_dat[15:0] <= #1 mcuCfg_CmdIf_wr_param[15:0] ; // 寄存器0x54/55h CmdIf_wr_dat[23:16] <= #1 0 ; CmdIf_wr_dat1[15:0] <= #1 mcuCfg_CmdIf_wr_param[15:0] ; // 寄存器0x54/55h CmdIf_wr_dat1[23:16] <= #1 0 ; mcuCfg_CmdIf_rd_param_ch1 <= #1 w_CmdIf_rd_dat0[15:0] ; // 寄存器0x63/64h mcuCfg_CmdIf_rd_param_ch2 <= #1 w_CmdIf_rd_dat1[15:0] ; // 寄存器0x63/64h mcuCfg_CmdIf_rd_param_ch3 <= #1 w_CmdIf_rd_dat2[15:0] ; // 寄存器0x63/64h mcuCfg_CmdIf_rd_param_ch4 <= #1 w_CmdIf_rd_dat3[15:0] ; // 寄存器0x63/64h // MCU读取CmdIf工作状态 mcuCfg_CmdIf_op_state <= #1 w_CmdIf_op_state ; // 寄存器0x52h bit1-0 mcuCfg_CmdIf_op_finish <= #1 w_CmdIf_op_finish ; // 寄存器0x52h bit7 mcuCfg_CmdIf_rw_dat_count <= #1 w_CmdIf_rw_dat_count ; // 寄存器0x70~73h end end //-------------------------------------------------------------------------------------------------------------- // State-10, 等待下一图片的首行数据缓存好后进行相关操作和配置(2828) FSM_CmdCtrl_WAIT_NXT_BMP_BUF_DONE: begin // 使能Cmd_buf(fifo)缓存数据 poc_host_Cmd_dat_ena <= #1 1; if (host_Cmd_dat_hs_wr_done_flag) begin fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_NXT_BMP_DO_CFG; end end //-------------------------------------------------------------------------------------------------------------- // State-11, 在下一图片数据发之前, 相关操作和配置(2828)(切图配置), 完成后进入数据发送状态 FSM_CmdCtrl_NXT_BMP_DO_CFG: begin // 根据MCU或host配置的不同的mipi tx模式, 进行相应操作 // 提供host配置接口 CmdIf_eclk_frq <= #1 hostCfg_CmdIf_eclk_frq ; CmdIf_op_type <= #1 hostCfg_CmdIf_op_type ; CmdIf_op_ena <= #1 hostCfg_CmdIf_op_ena ; CmdIf_reg <= #1 hostCfg_CmdIf_reg ; CmdIf_wr_dat[15:0] <= #1 hostCfg_CmdIf_wr_param ; CmdIf_wr_dat[23:16] <= #1 0 ; CmdIf_wr_dat1[15:0] <= #1 hostCfg_CmdIf_wr_param ; CmdIf_wr_dat1[23:16] <= #1 0 ; poc_hostCfg_CmdIf_op_finish <= #1 w_CmdIf_op_finish ; // 2828数据位宽为24bit mipi_Cmd_if_bus_type <= #1 1 ; // 使能host配置 // 当host配置完成, 则本操作结束, 进入数据传输状态 if (host_cfg_datu_param_done_flag) begin poc_host_cfg_datu_param_ena <= #1 0; //cnt_vs_tx_do_cfg_dly <= #1 0; fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_FPGA_TX_DAT; end else begin poc_host_cfg_datu_param_ena <= #1 1; //cnt_vs_tx_do_cfg_dly <= #1 cnt_vs_tx_do_cfg_dly; fsm_Cmd_ctrl <= #1 fsm_Cmd_ctrl; end // 传输模式设置 case (Cmd_dat_tx_mod) // 行tx模式 'd0: begin poc_datu_dat_tx_type <= #1 0; // 2828行传输模式 poc_datu_param_type <= #1 0; // 每帧传输前配置2828 (切图传下一图时用) end // 帧tx模式 'd1: begin poc_datu_dat_tx_type <= #1 1; // 2828帧传输模式 poc_datu_param_type <= #1 0; // 每帧传输前配置2828 (切图传下一图时用) end endcase end //-------------------------------------------------------------------------------------------------------------- // State-12, 停止状态 FSM_CmdCtrl_STOP: begin fsm_Cmd_ctrl <= #1 fsm_Cmd_ctrl; end //-------------------------------------------------------------------------------------------------------------- default: begin fsm_Cmd_ctrl <= #1 FSM_CmdCtrl_SEL_INIT_SRC; end endcase 这个代码的功能,用途,操作逻辑,状态切换逻辑,和详细的代码讲解

filetype

module dac7571 ( input clk , input rst_n , output scl_dac , inout sda_dac , output reg led ); `define SCL_POSEDGE (cnt == 7'd0) `define SCL_NEGEDGE (cnt == 7'd50) `define SCL_HIG_MID (cnt == 7'd25) `define SCL_LOW_MID (cnt == 7'd87) //时钟频率、寄存器地址的声明 parameter CLK_FRQ = 50_000_000 ; parameter SLAVE_ADDRESS = 8'b1010_0000; //写设备地址 parameter SLAVE_ADDRESS_R = 8'b1010_0001; //读设备地址 parameter CTRL_MSB_BYTE = 8'b0011_1111; //存储器地址 parameter DATA = 8'b1010_0101; //parameter DELAY_COUNT = CLK_FRQ/2000; //5ms延时周期 //reg reg [ 7:0] data_tx ; reg [ 7:0] data_rx ; reg [ 5:0] state ; reg [ 6:0] cnt ; reg SCL_r ; reg SDA_r ; reg SDA_en ; reg [ 3:0] write_byte_cnt ; reg [ 7:0] write_byte_reg ; reg wr_flag ; reg config_done ; //reg [ 31:0] parameter CNT_3SEC=CLK_FRQ*3-1 ; parameter CNT_1SEC=CLK_FRQ-1 ; wire write_start_flag_wire; //使能信号 reg [31:0]auto_read_write_cnt_reg; //计数器 assign write_start_flag_wire=(auto_read_write_cnt_reg==CNT_1SEC)?1'b1:1'b0; //状态机定时功能 always@(posedge clk or negedge rst_n)begin if(!rst_n)begin auto_read_write_cnt_reg<='d0; end else begin if(auto_read_write_cnt_reg<CNT_3SEC)begin auto_read_write_cnt_reg<=auto_read_write_cnt_reg+'d1; end else begin auto_read_write_cnt_reg<='b0; end end end always @(posedge clk or negedge rst_n) begin if(!rst_n) cnt <= 0; else begin if(cnt == 7'd124)//2500 / 20 cnt <= 0; else cnt <= cnt + 1'b1; end end always @(posedge clk or negedge rst_n) begin if(!rst_n) SCL_r <= 0; else begin if(cnt == 7'd0) SCL_r <= 1'b1; else if(cnt == 7'd50) SCL_r <= 1'b0; end end //定义的状态机状态 parameter IDLE = 6'd0 ; parameter STRAT_W = 6'd1 ; parameter WRITE_SLAVE_ADDR = 6'd2 ; parameter ACK_1 = 6'd3 ; parameter SEND_CTRL_BYTE_M = 6'd4 ; parameter ACK_2 = 6'd5 ; parameter SEND_DATA = 6'd6 ; parameter ACK_3 = 6'd7 ; parameter STOP_W = 6'd8 ; parameter DELAY = 6'd9 ; parameter STRAT_R2 = 6'd10 ; parameter CONTROL_BYTE_ADDR = 6'd11 ; parameter ACK_4 = 6'd12 ; parameter RECV_DATA = 6'd13 ; parameter NACK = 6'd14 ; parameter STOP_R = 6'd15 ; reg [25:0] wr_flag_cnt; always @(posedge clk or negedge rst_n) begin if(!rst_n) begin wr_flag_cnt <= 0; wr_flag <= 0; led <= 0; end else begin if(wr_flag_cnt[25]) begin wr_flag_cnt <= 0; wr_flag <= 1'b1; led <= 1'b0; end else if(wr_flag_cnt<='d167796) begin led <= 0; wr_flag_cnt <= wr_flag_cnt + 1'b1; wr_flag <= wr_flag; end else begin wr_flag_cnt <= wr_flag_cnt + 1'b1; wr_flag <= 1'b0; led <= 1'b1; end end end always @(posedge clk or negedge rst_n) begin if(!rst_n) begin state <= IDLE; write_byte_cnt <= 0; write_byte_reg <= 0; SDA_en <= 1'b0; config_done <= 1'b0; //wr_reg <= 0; end else if(wr_flag) begin state <= IDLE; write_byte_cnt <= 0; write_byte_reg <= 0; SDA_en <= 1'b0; config_done <= 1'b0; end else begin case(state) IDLE: begin //0 config_done <= 1'b0; SDA_en <= 1'b1; SDA_r <= 1'b1; if(led) state <= STRAT_W; else state <= IDLE; end STRAT_W : begin //1 if(`SCL_HIG_MID) begin SDA_r <= 0; write_byte_cnt <= 0; write_byte_reg <= SLAVE_ADDRESS; state <= WRITE_SLAVE_ADDR; end else begin state <= STRAT_W; end end WRITE_SLAVE_ADDR: begin //write slave address 2 if(`SCL_LOW_MID) begin case(write_byte_cnt) 0: SDA_r <= write_byte_reg[7]; 1: SDA_r <= write_byte_reg[6]; 2: SDA_r <= write_byte_reg[5]; 3: SDA_r <= write_byte_reg[4]; 4: SDA_r <= write_byte_reg[3]; 5: SDA_r <= write_byte_reg[2]; 6: SDA_r <= write_byte_reg[1]; 7: SDA_r <= write_byte_reg[0]; default: ; endcase write_byte_cnt <= write_byte_cnt + 1'b1; if(write_byte_cnt == 4'd8) begin write_byte_cnt <= 4'd0; SDA_en <= 1'b0; // wait ACK, so SDA as input state <= ACK_1; end else state <= WRITE_SLAVE_ADDR; end end ACK_1: begin //prepare to ctrl byte 3 if(`SCL_NEGEDGE) begin write_byte_reg <= CTRL_MSB_BYTE; SDA_en <= 1'b1; state <= SEND_CTRL_BYTE_M; end else state <= ACK_1; end SEND_CTRL_BYTE_M: begin //write 4 if(`SCL_LOW_MID) begin case(write_byte_cnt) 0: SDA_r <= write_byte_reg[7]; 1: SDA_r <= write_byte_reg[6]; 2: SDA_r <= write_byte_reg[5]; 3: SDA_r <= write_byte_reg[4]; 4: SDA_r <= write_byte_reg[3]; 5: SDA_r <= write_byte_reg[2]; 6: SDA_r <= write_byte_reg[1]; 7: SDA_r <= write_byte_reg[0]; default: ; endcase write_byte_cnt <= write_byte_cnt + 1'b1; if(write_byte_cnt == 4'd8) begin write_byte_cnt <= 4'd0; SDA_en <= 1'b0; // wait ACK, so SDA as input state <= ACK_2; end else state <= SEND_CTRL_BYTE_M; end end ACK_2: begin //5 if(`SCL_NEGEDGE) begin data_tx <= DATA; SDA_en <= 1'b1; state <= SEND_DATA; end else state <= ACK_2; end SEND_DATA: begin if(`SCL_LOW_MID) begin case(write_byte_cnt) 0: SDA_r <= data_tx[7]; 1: SDA_r <= data_tx[6]; 2: SDA_r <= data_tx[5]; 3: SDA_r <= data_tx[4]; 4: SDA_r <= data_tx[3]; 5: SDA_r <= data_tx[2]; 6: SDA_r <= data_tx[1]; 7: SDA_r <= data_tx[0]; default: ; endcase write_byte_cnt <= write_byte_cnt + 1'b1; if(write_byte_cnt == 4'd8) begin write_byte_cnt <= 4'd0; SDA_en <= 1'b0; // wait ACK, so SDA as input state <= ACK_3; end else state <= SEND_DATA; end end ACK_3: begin //5 if(`SCL_NEGEDGE) begin SDA_en <= 1'b1; SDA_r <= 1'b0; state <= STOP_W; end else state <= ACK_3; end STOP_W: begin //7 if(`SCL_HIG_MID) begin SDA_r <= 1'b1; state <= STRAT_R2; //delay_cnt <= 0; end else state <= STOP_W; end STRAT_R2 : begin //1 if(`SCL_HIG_MID) begin SDA_r <= 0; write_byte_reg <= SLAVE_ADDRESS_R; state <= CONTROL_BYTE_ADDR; end else begin state <= STRAT_R2; end end CONTROL_BYTE_ADDR: begin if(`SCL_LOW_MID) begin case(write_byte_cnt) 0: SDA_r <= write_byte_reg[7]; 1: SDA_r <= write_byte_reg[6]; 2: SDA_r <= write_byte_reg[5]; 3: SDA_r <= write_byte_reg[4]; 4: SDA_r <= write_byte_reg[3]; 5: SDA_r <= write_byte_reg[2]; 6: SDA_r <= write_byte_reg[1]; 7: SDA_r <= write_byte_reg[0]; default: ; endcase write_byte_cnt <= write_byte_cnt + 1'b1; if(write_byte_cnt == 4'd8) begin write_byte_cnt <= 4'd0; SDA_en <= 1'b0; // wait ACK, so SDA as input state <= ACK_4; end else state <= CONTROL_BYTE_ADDR; end end ACK_4: begin //5 if(`SCL_NEGEDGE) begin SDA_en <= 1'b0; state <= RECV_DATA; end else state <= ACK_4; end RECV_DATA: begin if(`SCL_HIG_MID) begin case(write_byte_cnt) 0:data_rx[7]<= sda_dac ; 1:data_rx[6]<= sda_dac ; 2:data_rx[5]<= sda_dac ; 3:data_rx[4]<= sda_dac ; 4:data_rx[3]<= sda_dac ; 5:data_rx[2]<= sda_dac ; 6:data_rx[1]<= sda_dac ; 7:data_rx[0]<= sda_dac ; endcase write_byte_cnt <= write_byte_cnt + 1'b1; if(write_byte_cnt == 4'd8) begin write_byte_cnt <= 4'd0; SDA_en <= 1'b1; // wait ACK, so SDA as input state <= NACK; end else state <= RECV_DATA; end end NACK: begin //5 if(`SCL_LOW_MID) begin SDA_en <= 1'b0; SDA_r <= 1'b0; state <= STOP_R; end else state <= NACK; end STOP_R: begin //7 if(`SCL_HIG_MID) begin config_done <= 1'b1; SDA_r <= 1'b1; state <= IDLE; end end endcase end end assign scl_dac = SCL_r; assign sda_dac = SDA_en ? SDA_r : 1'bz; ila_0 ila_0_debuge ( .clk(clk), // input wire clk .probe0({rst_n,sda_dac,led,scl_dac,state,wr_flag_cnt,wr_flag,config_done,write_byte_cnt,cnt,SDA_en,data_tx,data_rx}) // input wire [127:0] probe0 ); endmodule 接收数据错误

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