VHDL编程实践：从逻辑门到复杂系统

PDF文件

下载需积分: 0 | 278KB | 更新于2024-07-25 | 92 浏览量 | 举报收藏

立即下载

"该资源提供了一系列VHDL编程的实例，涵盖了从基本的组合逻辑到复杂的硬件系统设计，包括微处理器行为模型和内存模块。所有示例都可以使用符合IEEE标准的VHDL模拟器进行仿真，并且许多可以进行综合，适用于当前的综合工具。示例分为多个类别，如组合逻辑、计数器、移位寄存器、存储器、状态机、寄存器、系统、模数转换器和数模转换器等。" 在VHDL编程中，这是一种广泛使用的硬件描述语言，用于设计和验证数字电子系统。VHDL具有数据流、行为和结构三种不同的描述风格，使得设计者能够灵活地表达各种硬件行为。 1. **组合逻辑**：这部分包含了基本的逻辑门，如XOR门的三种描述方式——数据流风格、行为风格和结构风格。数据流风格强调信号的输入与输出关系；行为风格关注的是逻辑功能的行为描述；而结构风格则更接近实际电路的物理实现，由基本逻辑门构建。 2. **计数器**：计数器是数字系统中的常见元素，这些示例可能包括二进制计数器、模N计数器等，展示了如何用VHDL描述时序逻辑。 3. **移位寄存器**：移位寄存器可以执行数据的左移、右移或循环移位，它们在串行通信和数据处理中很重要。 4. **存储器**：这部分可能包含RAM、ROM或者FIFO等，展示了VHDL如何实现不同类型的存储单元。 5. **状态机**：状态机是描述复杂控制逻辑的关键工具，可以是同步或异步，Mealy型或Moore型，用于解释设备的控制流程。 6. **寄存器**：寄存器用于暂时存储数据，包括D型触发器、T型触发器等，它们是数字系统中的基础组件。 7. **系统**：这部分可能涉及到更复杂的系统级设计，如微处理器行为模型，这有助于理解系统级行为和接口。 8. **模数转换器（ADC）和数模转换器（DAC）**：这些是模拟和数字世界之间的桥梁，VHDL提供了描述它们的方法。 9. **算术运算**：VHDL可以描述加法器、乘法器等算术逻辑单元，支持进行基本的数值计算。通过这些实例，学习者不仅可以了解VHDL的基础语法，还能深入理解其在设计复杂数字系统中的应用。这些示例提供了丰富的实践素材，对于提升VHDL编程技能非常有帮助。

Examples of VHDL Descriptions

tin(i) <= '1';

end generate;

t1_size : if i > 0 generate

tin(i) <= q(i-1) and tin(i-1);

end generate;

end v1;

Counter using Multiple Wait Statements

This example shows an inefficient way of describing a counter.

--vhdl model of a 3-state counter illustrating the use

--of the WAIT statement to suspend a process.At each wait

--statement the simulation time is updated one cycle,transferring

--the driver value to the output count.

--This architecture shows that there is no difference between

--WAIT UNTIL (clock'EVENT AND clock = '1') and WAIT UNTIL clock = '1'

ENTITY cntr3 IS

PORT(clock : IN BIT; count : OUT NATURAL);

END cntr3;

ARCHITECTURE using_wait OF cntr3 IS

BEGIN

PROCESS

BEGIN

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 2;

END PROCESS;

END using_wait;

Counter using a Conversion Function

This counter uses a natural number to hold the count value and converts it into a bit_vector for output. Illustrates the use of a function.

--4-bit binary up counter with asynchronous reset 2/2/93

ENTITY cntr4bit IS

PORT(reset,clock : IN BIT; count : OUT BIT_VECTOR(0 TO 3));

END cntr4bit;

ARCHITECTURE dataflow OF cntr4bit IS

--interface function to generate output bit_vector from

--internal count value.

FUNCTION nat_to_bv(input : NATURAL; highbit : POSITIVE)

RETURN BIT_VECTOR IS

VARIABLE temp : NATURAL := 0;

VARIABLE output : BIT_VECTOR(0 TO highbit);

BEGIN

temp := input;

--check that input fits into (highbit+1) bits

ASSERT (temp <= (2**(highbit + 1) - 1))

REPORT "input no. is out of range" SEVERITY ERROR;

http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html (12 of 67) [23/1/2002 4:15:08 ]

Examples of VHDL Descriptions

--generate bit values

FOR i IN highbit DOWNTO 0 LOOP

IF temp >= (2**i)

THEN output(i) := '1';

temp := temp - (2**i);

ELSE output(i) := '0';

END IF;

END LOOP;

RETURN output;

END nat_to_bv;

--signal to hold current count value

SIGNAL intcount : NATURAL := 0;

BEGIN

--conditional natural signal assignment models counter

intcount <= 0 WHEN (reset = '1') ELSE

((intcount + 1) MOD 16) WHEN (clock'EVENT AND clock = '1')

ELSE intcount;

--interface function converts natural count to bit_vector count

count <= nat_to_bv(intcount,3);

END;

Quad 2-input Nand

Simple concurrent model of a TTL quad nand gate.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT00 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT00;

architecture VER1 of HCT00 is

begin

Y1 <= A1 nand B1 after 10 ns;

Y2 <= A2 nand B2 after 10 ns;

Y3 <= A3 nand B3 after 10 ns;

Y4 <= A4 nand B4 after 10 ns;

end VER1;

Dual 2-to-4 Decoder

A set of conditional signal assignments model a dual 2-to-4 decoder

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT139 is

port(A2, B2, G2BAR, A1, B1, G1BAR : in std_logic;

Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic);

end HCT139;

architecture VER1 of HCT139 is

begin

Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y11 <= '0' when (B1 = '0') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y12 <= '0' when (B1 = '1') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y13 <= '0' when (B1 = '1') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y20 <= '0' when (B2 = '0') and ((A2 = '0') and (G2BAR = '0')) else '1';

http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html (13 of 67) [23/1/2002 4:15:08 ]

Examples of VHDL Descriptions

Y21 <= '0' when (B2 = '0') and ((A2 = '1') and (G2BAR = '0')) else '1';

Y22 <= '0' when (B2 = '1') and ((A2 = '0') and (G2BAR = '0')) else '1';

Y23 <= '0' when (B2 = '1') and ((A2 = '1') and (G2BAR = '0')) else '1';

end VER1;

Quad D-Type Flip-flop

This example shows how a conditional signal assignment statement could be used to describe sequential logic (it is more common to use a process). The keyword 'unaffected' is equivalent to the 'null' statement in the sequential part

of the language. The model would work exactly the same without the clause 'else unaffected' attached to the end of the statement.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT175 is

port(D : in std_logic_vector(3 downto 0);

Q : out std_logic_vector(3 downto 0);

CLRBAR, CLK : in std_logic);

end HCT175;

architecture VER1 of HCT175 is

begin

Q <= (others => '0') when (CLRBAR = '0')

else D when rising_edge(CLK)

else unaffected;

end VER1;

Octal Bus Transceiver

This example shows the use of the high impedance literal 'Z' provided by std_logic. The aggregate '(others => 'Z')' means all of the bits of B must be forced to 'Z'. Ports A and B must be resolved for this model to work correctly (hence std_logic rather than

std_ulogic).

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT245 is

port(A, B : inout std_logic_vector(7 downto 0);

DIR, GBAR : in std_logic);

end HCT245;

architecture VER1 of HCT245 is

begin

A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');

B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');

end VER1;

Quad 2-input OR

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT32 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT32;

architecture VER1 of HCT32 is

begin

Y1 <= A1 or B1 after 10 ns;

Y2 <= A2 or B2 after 10 ns;

Y3 <= A3 or B3 after 10 ns;

Y4 <= A4 or B4 after 10 ns;

http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html (14 of 67) [23/1/2002 4:15:08 ]

剩余67页未读，继续阅读