TI SN75DPHY440SS：MIPI CSI-2 DPHY重定时器与特性详解

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TI-SN75DPHY440SS是一款高性能的MIPI DPHY（DSI-PHY）重定时器，专为满足高速串行接口（如CSI-2）的数据传输需求而设计。这款器件的核心特性包括： 1. **MIPI DPHY 1.1合规性** - SN75DPHY440SS符合MIPI Digital Physical Layer (PHY) 1.1标准，确保了与各种MIPI兼容设备的无缝通信。 2. **低成本电缆解决方案** - 通过集成的优化功能，可以降低系统总体成本，简化布线和信号完整性管理。 3. **高通道支持** - 在1.5 Gbps数据速率下，它能够支持多达4条独立的通道，适应多种高速串行接口应用，如CSI-2/DSI，其时钟频率范围可达100 MHz 至 750 MHz。 4. **低功耗设计** - 在休眠状态下，器件的功耗极低，有助于节能和延长电池寿命。 5. **双工LP模式** - 支持MIPIDSI双向低功耗（LP）模式，以减少功耗并延长设备待机时间。 6. **多种工作状态支持** - 包括ULPS（Ultra Low Power State）和LP（Low Power）状态，可根据应用灵活调整设备性能。 7. **可调输出** - 提供可调电压摆幅、TX预加重电平选项，以增强信号质量。 8. **RxEQ补偿** - 可调接收均衡（RxEQ）功能用于补偿信号干扰（ISI），提高信号传输的稳定性。 9. **边缘速率控制** - 可配置的边沿速率控制允许精确调整信号传输的同步。 10. **数据和时钟补偿** - 动态补偿机制确保数据和时钟信号在长距离传输中的准确对接。 11. **ESD保护** - 配备3kV ESD（Electrostatic Discharge）保护，确保设备在电气噪声环境中的可靠性。 12. **宽温范围** - 工业级版本SN65DPHY440SS工作温度范围为-40°C至85°C，商业级SN75DPHY440SS则为0°C至70°C，确保在各种环境条件下稳定运行。这款重定时器适用于一系列电子设备，如笔记本电脑、翻盖手机和平板电脑，特别是对摄像头应用，因为文档中特别提到了用于CSI-2 Source（相机）和CSI-2 Sink（APU）的接口。它广泛应用于需要高速、低功耗和可靠串行数据传输的场景，如图像传感器接口和移动设备内部通信。在实际设计中，设计者应参考最新的英文版数据手册SLLSEO9获取最准确和完整的产品规格和使用指南。

SN65DPHY440SS

SN75DPHY440SS

www.ti.com.cn

ZHCSES3C –MARCH 2016–REVISED AUGUST 2019

6.5 Electrical Characteristics, Power Supply

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

PACTIVE1_SS

Power under normal operation for 4 data

lanes + clock.

DPHY Lanes at 1 Gbps; V

supply stable,

= 1.8 V;

150 mW

PACTIVE2_SS

Power under normal operation for 2 data

lanes + clock.

DPHY Lanes 1 Gbps; V

supply stable,

= 1.8 V;

115 mW

PLP11_SS LP11 Power

All DPHY lanes in LP11; V

supply stable;

= 1.8 V;

14 mW

PRSTN_SS RSTN Power

RSTN held in asserted state (low); V

supply stable; V

= 1.8 V;

0.75 mW

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Standard IO (RSTN, ERC, EQ, CFG[1:0])

Low-level control signal input voltage 0.2 x V

Mid-level control signal input voltage V

/ 2 V

High-level control signal input voltage 0.8 x V

Floating Voltage V

= High Impedance V

/ 2 V

Low level output voltage (open-drain).

ERC (SDA) only

At I

max. 0.2 x V

Low Level Output Current 3 mA

High level input current ±36 µA

Low level input current ±36 µA

Internal pull-up resistance 100 kΩ

Internal pull-down resistance 100 kΩ

(RSTN)

RSTN control input pullup resistor 300 kΩ

MIPI Input Leakage (DA1P/N, DA2P/N, DA3P/N, DACP/N)

lkg

Input failsafe leakage current

= 0 V; V

= 0 V; MIPI DPHY pulled

up to 1.35 V

–65 65 µAV

MIPI DPHY HS RECIEVER INTERFACE (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N)

(CM-RX_DC)

Differential Input Common-mode voltage

HS Receive mode

(CM-RX)

= (V

A x P

+ V

A x N

)/2 70 330 mV

| V

| HS Receiver input differential voltage | V

| = |V

A x P

– V

A x N

| 70 mV

IH(HS)

Single-ended input high voltage 460 mV

IL(HS)

Single-ended input low voltage –40 mV

(DIFF-HS)

Differential input impedance 80 100 125 Ω

(RXEQ0)

Rx EQ gain when EQ/SCL pin ≤ V

0 dB

(RXEQ1)

Rx EQ gain when EQ/SCL pin = V

At 750 MHz 2.5 dB

(RXEQ2)

Rx EQ gain when EQ/SCL pin ≥ V

At 750 MHz 5 dB

MIPI DPHY LP Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N, DB0P/N)

(LPIH)

LP Logic 1 Input Voltage 880 mV

(LPIL)

LP Logic 0 Input voltage 550 mV

(HYST)

LP Input Hysteresis 25 mV

MIPI DPHY HS Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N)

(CMTX)

HS Transmit static common-mode

voltage

(CMTX)

= (V

(BP)

+ V

(BN)

) / 2 150 200 300 mV

|∆V

(CMTX) (1,0)

VCMTX mismatch when output is

Differential-1 or differential-0.

∆V

(CMTX) (1,0)

= (V

(CMTX) (1)

– V

(CMTX) (0)

) /2 5 mV

OD(VD0)

HS Transmit differential voltage for

CFG0 = 2’b00 with TX pre-emphasis

disabled or for non-transition bit when

TX pre-emphasis is enabled.

| = |V

(DP)

- V

(DN)

| 140 180 220 mV

OD(VD1)

HS Transmit differential voltage for

CFG0 = V

with TX pre-emphasis

disabled or for non-transition bit when

TX pre-emphasis is enabled.

| = |V

(DP)

- V

(DN)

| CFG0 = V

160 200 250 mV

SN65DPHY440SS

SN75DPHY440SS

ZHCSES3C –MARCH 2016–REVISED AUGUST 2019

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OD(VD2)

HS Transmit differential voltage for

CFG0 = V

with TX pre-emphasis

disabled or for non-transition bit when

pre-emphasis is enabled..

| = |V

(DP)

- V

(DN)

| CFG0 ≥ V

170 220 270 mV

|∆V

mismatch when output is

differential-1 or differential-0.

∆V

= |∆V

O(D1)

| - |∆V

O(D0)

| 14 mV

OH(HS)

HS Output high voltage for non-

transition bit.

CFG0 ≥ V

HS Pre = 2.5 dB 430 mV

(PRE1)

Pre-emphasis Level for HSTX_PRE =

2’b00.. Refer to Figure 3

PRE = 20 x LOG (V

OD(TBx)

/ V

OD(VDX)

) 1.5 dB

(PRE2)

Pre-emphasis level for HSTX_PRE =

2’b1X. Refer to Figure 3

PRE = 20 x LOG (V

OD(TBx)

/ V

OD(VDX)

) 2.5 dB

MIPI DPHY LP Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N, DA0P/N)

(LPOH)

LP Output High Level 1.1 1.2 1.3 V

(LPOL)

LP Output Low Level –50 50 mV

IH(CD)

LP Logic 1 contention threshold 450 mV

IL(CD)

LP Logc 0 contention threshold 200 mV

O(LP)

Output Impedance of LP transmitter 110 Ω

6.7 Timing Requirements

MIN NOM MAX UNIT

I2C (ERC (SDA), EQ (SCL))

HD;STA

Hold Time (repeated) START condition. After this period, the first clock pulse is generated 4 µs

LOW

Low period of SCL clock 4.7 µs

HIGH

High period of SCL clock 4 µs

SU;STA

Setup time for a repeated START condition 4.7 µs

HD;DAT

Data hold time 5 µs

SU;DAT

Data setup time 4 µs

SU;STO

Setup time for STOP condition 4 µs

BUF

Bus free time between a STOP and START condition 4.7 µs

MIPI DPHY HS Interface

HSPD

Propagation delay from DA to DB. 4 + 12ns 4 + 40ns UI

DBC_DCYCLE

DAC to DBC output duty cycle distortion percentage

750 MHz clock with 50%-50%

duty cycle at DAC input.

–5 5 %

SKEW-TX-1G

Data to Clock variation from 0.5UI. Refer to Figure 2 Datarate ≤ 1 Gbps –0.1 0.1 UI

SETUP-RX-1G

Data to Clock setup time. Refer to Figure 2 Datarate ≤ 1 Gbps 0.1 UI

HOLD-RX-1G

Clock to data hold time. Refer to Figure 2 Datarate ≤ 1 Gbps 0.1 UI

SKEW-TX-1P5G

Data to Clock variation from 0.5UI. Refer to Figure 2 Datarate > 1 Gbps –0.15 0.15 UI

SETUP-RX-

1P5G

Data to Clock setup time. Refer to Figure 2 Datarate > 1 Gbps 0.15 UI

HOLD-RX-1P5G

Clock to data hold time. Refer to Figure 2 Datarate > 1 Gbps 0.15 UI

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TI SN75DPHY440SS：MIPI CSI-2 DPHY重定时器与特性详解

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