Advanced packaging is coming into sharp focus in today’s AI era. Once regarded as an afterthought in the chip making process, advanced packaging now holds the key to better power, performance, area, and cost efficiency. One approach that’s making these improvements possible is the use of redistribution layers, or RDLs for short.
Although not all AI packages use RDLs, they’re commonly used in Fan-Out Wafer Level Packaging (FoWLP), Chip-on-Wafer-on-Substrate (CoWoS) designs, and Embedded Wafer Level Ball Grid Arrays (eWLB). But don’t worry too much about the package structures. In this article, we’ll mainly focus on the RDLs themselves.
The History of Routing Technologies
I spoke with Mark Gerber from ASE and Chuck Woychik from NHanced Semiconductors to better understand RDLs. To help contextualize the reasons why RDL is important, they gave me an overview of the history of routing technology.
Essentially, routing provides a way for the components in a package to communicate. For example, a package might have a high bandwidth memory (HBM) stack placed next to a GPU, and they need a way to transfer information between one another.
When it comes to routing, the most basic way to do it is through a printed circuit board (PCB). This is the least advanced form of routing technology; however, it’s still used for lower-end applications because it’s cost-effective and easy to manufacture at high volumes compared to other types of routing technologies.
A step up from PCBs are traditional substrate technologies that provide a platform for chip mounting, signal transmission, and heat dissipation. They are typically made from a Bismaleimide-Triazine (BT) resin that acts as the “core” material, and a major benefit of using a substrate is to improve the overall interconnect density. By increasing the interconnect density, the semiconductor industry can achieve better signal speed and power efficiency while also reducing device size.
From there, the next level of routing is buildup technology based on a core material. It enables even better interconnect density than using traditional substrate or PCB technology alone. Of the three routing technologies discussed so far, this is the most advanced.
For ultra-advanced applications like AI, Gerber explained that the industry needs to shift to a wafer-based substrate technology to achieve the best possible interconnect densities. This is where RDL comes in. Although the industry may use the term “RDL” to generally reference any type of routing layer, it’s a term that’s technically refers only to the wafer-level routing process. This is the process used for FoWLP, CoWoS, and so on.
To understand how all of this ties into the bigger picture, it’s also important to discuss line/space capabilities. In this industry, line/space refers to the dimensions of the metal traces (lines) and the gaps (spaces) between the lines. Smaller line/space means greater interconnect density, which is what the industry wants. For example, a basic PCB structure usually falls somewhere between 60-100µm line/space.
In contrast, a traditional substrate technology mounted on a PCB can typically achieve 20µm line/space. Meanwhile, a buildup technology can reach approximately 12µm line/space, and this is about the limit without moving to a wafer-based technology. By moving to a wafer-based process, the industry can get down to 1.5µm line/spaces on average. Woychick also explained that achieving submicron line/space is also technically possible, but that requires a copper damascene process. We won’t get into that here, but it’s something to be aware of.
All of this to say, that RDLs are fundamentally important because they address the complex routing and design requirements demanded by advanced applications like AI. As the number of I/O signals increases, the industry needs to route more within the package. RDL reduces the lines and spaces, which is key for meeting today’s demands.
Types of RDL Integration
Now that we touched on what redistribution layers are and why they matter, let’s discuss the two main ways that RDL can be integrated into a package. The first way is on a carrier like silicon.
With the silicon carrier approach, the RDL is always added to the top of the silicon, and depending on the application, it’s sometimes added to the bottom as well. The silicon acts as the medium for holding the RDLs, and this approach is similar to the substrate approach described previously. Glass can be used as a carrier as well, but we won’t cover that today.
The other method for RDL application is to forego the carrier entirely and apply the RDL on its own.
Oftentimes, you’ll see the carriers (or RDL if no carrier is present), referred to as an interposer. However, this is a broad term. When people use this word, they’re usually referring to silicon or RDL specifically, but it can also be used broadly to describe any electrical interface that connects two or more components.
Communication Between Redistribution Layers
As mentioned previously, the purpose of RDL is to enable communication between HBM stacks and xPUs while reducing line/space to improve interconnect density. With this in mind, both methods for applying RDL achieve this in different ways.
For instance, when silicon interposers are used, through silicon vias (TSVs) are used to vertically connect each RDL structure.
In contrast, RDL structures without a silicon carrier use layers of polyamide material and copper to reroute connections to different areas of the chip. In this case, the interposer is the polyamide material, and the polyamide layers are vertically connected by copper vias.
It’s also important to touch on the aspect ratio of the vias themselves, as this plays a major role in interconnect density. When it comes to an RDL stack without a carrier, the via aspect ratios are typically around 1:1. This is because each polyamide layer is around 5-7µm thick, and the diameter of a copper via is also around 7µm, making the total via aspect ratio 1:1 or less.
However, this structure might also use a thick, reusable “carrier” that’s sole purpose is to keep the RDLs flat. When using a carrier, the RDLs might have a total thickness of 50µm or less depending on the number of layers. The carrier is important for panel-level packaging (PLP), and we’ll touch more on this later.
But even despite the reusable carrier, RDL alone still offers huge improvements over TSVs, which have an average aspect ratio of around 10:1. This is because the silicon interposer alone has a minimum thickness of 100µm. If the silicon interposer target is less than 100µm, manufacturing and handing challenges will arise.
There is also impedance losses associated with larger via sizes, and mitigating these losses can make eliminating the silicon interposer a more attractive option for certain AI applications. This is because the interconnect distance between each redistribution layer is shorter, and there are electrical benefits that come with that.
Bridge Die vs. Adding Redistribution Layers
Although it may seem that using RDLs without a silicon carrier may be the best approach, routing them can quickly become extremely complex as the number of layers increases. Right now, most FoWLP structures, for example, are using 1-4 redistribution layers. For context, many fan-out package designs only use a single layer, but higher-end applications can reach up to four. On top of this, Gerber explained that layer count is quickly increasing to keep up with higher density HBM integration and routing requirements.
While more redistribution layers can open new doors for routing, integrating four or more HBM stacks that communicate with the xPU can be extremely difficult. This is because each memory component can have more than 5,000 I/Os that require routing.
Nevertheless, routing this many I/Os can be achieved in two main ways. One is by using multiple RDLs and simply accepting their complex routing requirements, and another is by using a bridge die. For more complex packages, both are often used in tandem.
Using a bridge die can be an attractive option, but this only works for RDL structures that use silicon interposers to begin with. A bridge die is a small piece of silicon that’s used for routing, and it does exactly what its name suggests – it acts as a “bridge” between the HBM or xPU. The bridge has submicron line/space capabilities, and it’s embedded between the two components (Figure 1).
Bridge die can achieve dense routing without the complexities associated with RDL alone. For example, if a package has four HBM stacks, it will also have four bridge die connecting the stacks to the xPU. Because so much of the routing is being done by the bridge die, these packages only require one RDL.
Conversely, eliminating bridge die can be more cost effective, but more RDLs must be added in their place. Technically, 4-6 RDLs can be used instead, but this can also make routing difficult due to the high number of I/Os. In addition, these layers can only route around two HBM stacks, posing limitations for AI.
However, if the industry is going to keep up with additional integration, more routing layers will eventually allow for HBM stacks in the package. This will be crucial for advancing the roadmap of AI, and it’s something the industry is actively working on today.
Although there’s no perfect solution, companies need to weigh the pros and cons of using bridge die versus additional RDLs. Which one they choose will vary based on their specific application.
The Near-Term Future of RDL
Right now, PLP is emerging as a potential solution for furthering RDL without needing a silicon carrier. As previously mentioned, these carriers are used to keep the layers flat and safely handle the delicate wafers during RDL steps. Panel level packaging uses a rectangular panel as a carrier, as opposed to the traditionally used round panel.
Moving to rectangular panels matters for RDL development because PLP allows for each RDL layer to be manufactured at a higher volume. Round wafers waste material around the edges, and panels provide a way to mitigate this. This in turn, can help decrease the overall manufacturing cost while improving line efficiency.
Even though PLP has its own challenges, its adoption is skyrocketing. Earlier this year, Yole Group reported that the compound annual growth rate (CAGR) for PLP is more than 27%.
Closer collaboration across the value chain is also leading to advancements in RDL. Instead of viewing semiconductor packaging as an isolated process, rising demands driven by AI are incentivizing experts from multiple disciplines to work together to solve challenges brought on by mounting complexity. Real-world examples of collaborative efforts include Onto Innovation’s PACE Center and Resonac’s US-JOINT consortium.
To Summarize
Increasing layer count can eventually allow for HBM stacks in the package. Generally speaking, this is what the industry wants. More memory means more data can be exchanged at faster speeds, which is essential for executing complex AI tasks.
Although adding more RDLs can make it difficult to route the I/Os that communicate with the xPU, it’s being done successfully, nonetheless. However, as it stands today, using a bridge die and silicon interposer may be a simpler solution overall.
