Dependency vs Hazards

In pipelined processors, dependencies indicate the order in which instructions must be executed because some instructions rely on the results of others. Hazards, on the other hand, are problems that occur due to these dependencies, potentially delaying or stalling the pipeline. In simple terms:

• Dependency defines the order of tasks.
• Hazard is the trouble that arises because of that order.

Example 1: Is DATA Dependency Always Create RAW Hazards?

→ May or may not
→ Now RAW Hazards Concept Along with Data Dependencies.

Data Dependencies in this question:

I₅ ← I₁
I₆ ← I₁

Explanation:

• Now in this question 2 there is a 2 Data Dependency b/w (I₅ ← I₁) & (I₆ ← I₁).
• Now check it creates RAW Hazards (Stalls) or not?

RISC: 5 stage IF, ID, EX, MA, WB

• At CC5 (Clock cycle 5) we getting the value of Register R₀ of Instruction I₁.
• After CC5, if R₀ is need, then there is no Hazards (No stalls).

Example 2: Data Dependency Creating RAW Hazard

Execution: one instruction in a normal pipeline manner.
If there is a stall/bubble/extra cycle due to dependency, it creates stalls.

Data Dependencies in this question:

I₁ → I₂ (I₂ depends on result of I₁)

RISC 5 Stage: IF, ID, EX, MA, WB

Explanations:

• At CC3: I₂ read wrong value of r₀
• At CC4: I₂ read wrong value of r₀
• At CC5: I₂ read wrong value of r₀

• The correct value for r₀ becomes available only at the end of CC5 (after write-back of I₁).

Hence, I₂ must be stalled for 3 cycles (inserting bubbles in the pipeline) until the correct value of r₀ is ready.