Operand Forwarding/Bypassing Last Updated : 13 Nov, 2025 Comments Improve Suggest changes Like Article Like Report Operand forwarding is a technique used in pipelined processors to minimise data dependency stall cycles. It uses special hardware to detect a conflict and then avoid it by routing the data through special paths between pipeline segments.It is also referred to as data piping.This mechanism states that we use a buffer between each stage to hold the intermediate result so that the dependent instruction can access the new data from the buffer before it is updated in the register file.Instructions:I1 : r2 ← r1 + r2I2 : r3 ← r2 × r4Without Operand ForwardingIn this case, the processor cannot use the result of an instruction until it is written back to the register file, causing pipeline stalls due to data dependency between consecutive instructions.Pipeline Table What HappensI2 starts fetching and decoding right after I1.When I₂ reaches the Execute (EX) stage (cycle CC4), it needs r₂ as an operand.I1 has just finished EX in CC3 but hasn’t written the new value of r2 back to the register file until the Write Back (WB) stage in CC5.Data Hazard: I2 cannot use the new r2 during CC4, because it isn’t updated yet.Result: The pipeline inserts 3 stalls (bubbles) to wait until I1 completes WB and r2 is updated. Only then can I2 execute.With Operand ForwardingHere, special hardware forwards the computed result directly from one pipeline stage to another, allowing dependent instructions to execute without waiting for the register write-back and thus eliminating stalls. What HappensI₂ starts as before.When I₂ reaches EX in CC4, I₁ has just finished EX in CC3.Forwarding Path: Operand forwarding hardware detects that the new value of r2 will be needed and directly passes I1's EX output to I2's EX stage input, without waiting for WB.No Stalls: I2 receives the correct r2 value immediately, so the pipeline proceeds smoothly. No stall cycles are needed.Key PointsStall Cycles (without forwarding): The processor halts the pipeline for I2 until r2 is written back to the register file.Forwarding: Hardware moves the freshly computed value directly to the dependent instruction’s execution stage as soon as it is available.Benefit: Faster instruction throughput, fewer wasted cycles, improved pipeline performance. Create Quiz Comment V vijaylcqkp Follow 0 Improve V vijaylcqkp Follow 0 Improve Article Tags : Computer Organization & Architecture Explore Basic Computer InstructionsWhat is a Computer? 6 min read Issues in Computer Design 1 min read Difference between assembly language and high level language 2 min read Addressing Modes in 8086 7 min read Difference between Memory based and Register based Addressing Modes 4 min read Von Neumann Architecture 5 min read Harvard Architecture 3 min read Interaction of a Program with Hardware 3 min read Simplified Instructional Computer (SIC) 4 min read Instruction Set used in simplified instructional Computer (SIC) 1 min read Instruction Set used in SIC/XE 2 min read RISC vs CISC 3 min read Vector processor classification 5 min read Essential Registers for Instruction Execution 3 min read Single Accumulator Based CPU Organization 3 min read Stack based CPU Organization 3 min read Machine Control Instructions in Microprocessor 4 min read Very Long Instruction Word (VLIW) Architecture 3 min read Input and Output SystemsPrimary Instruction Cycles 4 min read Machine Instructions 5 min read Instruction Formats 6 min read Difference between 2-address instruction and 1-address instructions 4 min read Difference between 3-address instruction and 0-address instruction 4 min read Register content and Flag status after Instructions 3 min read Debugging a machine level program 3 min read Vector Instruction Format in Vector Processors 7 min read Vector Instruction Types 4 min read Instruction Design and FormatALU Functions and Bus Organization 5 min read Computer Arithmetic | Set - 1 5 min read Computer Arithmetic | Set - 2 4 min read 1's Complement Representation vs 2's Complement Representation 4 min read Restoring Division Algorithm For Unsigned Integer 4 min read Non-Restoring Division For Unsigned Integer 3 min read Booth's Algorithm 4 min read How the Negative Numbers are Stored in Memory? 2 min read Microprogrammed ControlMicro-Operation 3 min read Instruction Set Architecture and Microarchitecture 3 min read Program Control Instructions 4 min read Difference between CALL and JUMP instructions 5 min read Hardwired and Micro-programmed Control Unit 3 min read Implementation of Micro Instructions Sequencer 4 min read Performance of Computer in Computer Organization 5 min read Introduction to Control Unit and its Design 5 min read Computer Organization | Amdahl's law and its proof 2 min read Subroutine: Nesting and Stack memory 3 min read Different Types of RAM (Random Access Memory ) 8 min read Random Access Memory (RAM) and Read Only Memory (ROM) 8 min read 2D and 2.5D Memory organization 4 min read Input and Output OrganizationPriority Interrupts 5 min read I/O Interface (Interrupt and DMA Mode) 4 min read DMA Controller 8257/8237 2 min read Computer Organization | Asynchronous input output synchronization 7 min read Programmable peripheral interface 8255 4 min read Synchronous Data Transfer in Computer Organization 4 min read Introduction of Input-Output Processor 5 min read MPU Communication in Computer Organization 4 min read Memory Mapped I/O and Isolated I/O 5 min read Memory OrganizationIntroduction to memory and memory units 2 min read Memory Hierarchy Design and its Characteristics 6 min read Register Allocations in Code Generation 6 min read Cache Memory 4 min read Cache Organization | Set 1 (Introduction) 3 min read Multilevel Cache Organisation 6 min read Difference between RAM and ROM 7 min read Difference Between CPU Cache and TLB 4 min read Introduction to Solid-State Drive (SSD) 4 min read Read and Write operations in Memory 3 min read PipeliningInstruction Level Parallelism 5 min read Execution and Throughput 5 min read Pipelining Types and Stalling 3 min read Computer Organization and Architecture | Pipelining | Set 2 (Dependencies and Data Hazard) 6 min read Last Minute Notes Computer Organization 15+ min read Like