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Operand Forwarding/Bypassing

Last Updated : 13 Nov, 2025
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Operand forwarding is a technique used in pipelined processors to minimise data dependency stall cycles. It uses special hardware to detect a conflict and then avoid it by routing the data through special paths between pipeline segments.

  • It is also referred to as data piping.
  • This mechanism states that we use a buffer between each stage to hold the intermediate result so that the dependent instruction can access the new data from the buffer before it is updated in the register file.

Instructions:

I1 : r2 ← r1 + r2

I2 : r3 ← r2 × r4

Without Operand Forwarding

In this case, the processor cannot use the result of an instruction until it is written back to the register file, causing pipeline stalls due to data dependency between consecutive instructions.

Pipeline Table

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What Happens

  • I2 starts fetching and decoding right after I1.
  • When I₂ reaches the Execute (EX) stage (cycle CC4), it needs r₂ as an operand.
  • I1 has just finished EX in CC3 but hasn’t written the new value of r2 back to the register file until the Write Back (WB) stage in CC5.
  • Data Hazard: I2 cannot use the new r2 during CC4, because it isn’t updated yet.
  • Result: The pipeline inserts 3 stalls (bubbles) to wait until I1 completes WB and r2 is updated. Only then can I2 execute.

With Operand Forwarding

Here, special hardware forwards the computed result directly from one pipeline stage to another, allowing dependent instructions to execute without waiting for the register write-back and thus eliminating stalls.

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What Happens

  • I₂ starts as before.
  • When I₂ reaches EX in CC4, I₁ has just finished EX in CC3.
  • Forwarding Path: Operand forwarding hardware detects that the new value of r2 will be needed and directly passes I1's EX output to I2's EX stage input, without waiting for WB.
  • No Stalls: I2 receives the correct r2 value immediately, so the pipeline proceeds smoothly. No stall cycles are needed.

Key Points

  • Stall Cycles (without forwarding): The processor halts the pipeline for I2 until r2 is written back to the register file.
  • Forwarding: Hardware moves the freshly computed value directly to the dependent instruction’s execution stage as soon as it is available.
  • Benefit: Faster instruction throughput, fewer wasted cycles, improved pipeline performance.

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