Translation Lookaside Buffer (TLB)

The Translation Lookaside Buffer (TLB) is a high-speed hardware cache situated inside or near the Memory Management Unit (MMU). It stores the most recently used mappings between Virtual Page Numbers (VPNs) and Physical Frame Numbers (PFNs), reducing the need for frequent page table lookups.

• Acts as a quick reference for recent virtual-to-physical address translations.
• Significantly speeds up memory access by minimizing main memory lookups.
• Enhances overall CPU performance and efficiency in address translation.

Problem of Access Time in Paging

Let’s first understand where the delay originates. When the CPU generates a virtual address, it must be translated into a physical address before accessing main memory. The page table, stored in memory, maintains this mapping between Virtual Page Numbers (VPNs) and Physical Frame Numbers (PFNs).

Without TLB: Two Memory Accesses per Reference

1. The CPU accesses the page table (in memory) to find the frame number corresponding to the virtual page.
2. Then, it accesses the main memory again to fetch the actual data.

Thus, every memory operation effectively needs two memory accesses, slowing down execution significantly.

Storing Page Table in Registers

Initially, one might think of keeping the page table in CPU registers to speed up the process since registers are the fastest storage available. However, this is impractical because:

• Registers are limited in number (typically only a few hundred or thousand entries).
• For large programs, the page table can contain millions of entries — e.g., for a 32-bit address space with 4 KB pages, over 1 million PTEs may be needed.

Therefore, the entire page table cannot fit into registers. The solution is to store the page table in main memory, but to use a small, fast cache (the TLB) for frequently accessed entries.

Architecture of the TLB

The TLB is typically a small associative or set-associative cache, allowing fast parallel searches. Each TLB entry contains several key fields:

This structure allows the TLB to serve multiple processes efficiently, avoiding confusion between their memory spaces.

Working of the TLB

Let’s see how the TLB functions during a memory access:

Step 1: CPU Generates Virtual Address

The CPU divides the virtual address into two parts:

• Page Number (P): used for lookup.
• Offset (d): used to locate data within the page.

Step 2: TLB Lookup

The TLB is searched in parallel for a matching Page Number (P) and ASID.

TLB Hit

• If a matching entry is found, the corresponding Frame Number (F) is retrieved immediately.
• The physical address is formed by combining F and the offset (d).
• The memory access proceeds without consulting the page table, leading to fast access.

TLB Miss

• If the entry is not found in the TLB, the CPU (or operating system) must look up the page table in main memory to get the correct Frame Number (F).
• The new mapping (P → F) is then loaded into the TLB for future use.
• If the TLB is full, a replacement policy (such as LRU, FIFO, or MFU) decides which old entry to replace.

Example

1. The CPU generates a virtual address 0x1234.
2. It splits the address into: Page Number = 0x12 and Offset = 0x34.
3. The TLB is searched for Page 0x12.
   • If found (TLB Hit): The corresponding Frame Number = 0x09 is retrieved, forming the Physical Address = 0x0934.
   • If not found (TLB Miss): The CPU accesses the page table in main memory to get the frame number, updates the TLB with this new entry, and then proceeds to access the required data in memory.

Effective Memory Access Time (EMAT)

To quantify the improvement TLB provides, we calculate the Effective Memory Access Time (EMAT):

EMAT = h × (c + m) + (1 − h) × (c + n × m)

Where:

• h: TLB hit ratio (probability of finding the entry in the TLB)
• c: TLB access time
• m: Main memory access time
• n: Number of memory accesses required on a TLB miss (usually 2)

Example Calculation

If TLB access time = 10 ns, memory access time = 100 ns, and hit ratio = 0.9:

EMAT = 0.9* (10 + 100) + (1−0.9) * (10 + 2 × 100) = 111 ns

Without TLB, it would take around 200 ns. Thus, the TLB nearly halves the effective access time.