Full Adder using Verilog HDL

A full adder is a digital circuit in Verilog HDL that adds three binary numbers. It has two inputs for the numbers to be added, A and B, and one Carry-In input, Cin. The outputs are Sum, S, and Carry-Out, Cout. A full adder has been implemented using Verilog as shown in the previously shared code snippet.

Problem Statement

Write a Verilog HDL to design a Full Adder. Let's discuss it step by step as follows.

Step-1
Concept :

Full Adder is a digital combinational Circuit which is having three input a, b and cin and two output sum and cout. Below Truth Table is drawn to show the functionality of the Full Adder.

Step-2 :
Truth Table -

Step-3 :
Verilog HDL code for Full Adder (Design Part) -

// Code your design : Full Adder
module full_add(a,b,cin,sum,cout);
  input a,b,cin;
  output sum,cout;
  wire x,y,z;
 
// instantiate building blocks of full adder 
  half_add h1(.a(a),.b(b),.s(x),.c(y));
  half_add h2(.a(x),.b(cin),.s(sum),.c(z));
  or o1(cout,y,z);
endmodule : full_add

// code your half adder design             
module half_add(a,b,s,c); 
  input a,b;
  output s,c;
 
// gate level design of half adder  
  xor x1(s,a,b);
  and a1(c,a,b);
endmodule :half_add

Step-4 :
Test bench -

// Code your testbench here
module full_add_tb;
  reg a,b,cin;
  wire sum,cout;
 
// instantiate the DUT block  
  full_add f1(.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));
 
// this particular line is added to dump the file on online simulator
  initial begin $dumpfile("full_tb.vcd");$dumpvars(); end

// insert all the inputs 
  initial begin a=1'b1;  #4; a=1'b0;#10 $stop();end
  initial begin b=1'b1; forever #2 b=~b;end
  initial begin cin=1'b1;forever #1 cin=~cin; #10 $stop();end

// monitor all the input and output ports at times 
// when any of the input changes its state

 initial begin $monitor(" time=%0d A=%b B=%b 
                          Cin=%b Sum=%b Cout=%b",$time,a,b,cin,sum,cout);end
 endmodule : full_add_tb

Step-5 :
Expected Output -

time=0 A=1 B=1 Cin=1 Sum=1 Cout=1
time=1 A=1 B=1 Cin=0 Sum=0 Cout=1
time=2 A=1 B=0 Cin=1 Sum=0 Cout=1
time=3 A=1 B=0 Cin=0 Sum=1 Cout=0
time=4 A=0 B=1 Cin=1 Sum=0 Cout=1
time=5 A=0 B=1 Cin=0 Sum=1 Cout=0
time=6 A=0 B=0 Cin=1 Sum=1 Cout=0
time=7 A=0 B=0 Cin=0 Sum=0 Cout=0
time=8 A=0 B=1 Cin=1 Sum=0 Cout=1
time=9 A=0 B=1 Cin=0 Sum=1 Cout=0
time=10 A=0 B=0 Cin=1 Sum=1 Cout=0
time=11 A=0 B=0 Cin=0 Sum=0 Cout=0
time=12 A=0 B=1 Cin=1 Sum=0 Cout=1
time=13 A=0 B=1 Cin=0 Sum=1 Cout=0

Advantage of Implementing a Full Adder in Verilog HDL

• Effective representation : This is because High Level Description of Circuit Behavior is possible with Verilog HDL, thus allowing for ease in the modeling of intricate digital circuits like a Full Adder.
• Uniformity : With the help of this language, one can describe hardware in a standard manner that promotes reusability and portability across various platforms.
• Shortened development duration : This means that there are fewer resources dedicated to carrying out these activities when using Verilog compared with other methods, due to its ability to simplify design procedures and enhance rapid prototyping of digital circuits.
• Simulational and Confirmational Perspectives : With Verilog, simulation and verification tools are supported to validate the design before implementing it on the physical hardware that has a guarantee of being functional and reliable.
• Adjustable design : Without necessitating a brand-new approach, Verilog ensures that circuits can be changed and improved with ease.

Applications of a Full Adder in Digital Systems

• Arithmetic Operations : For doing addition processes on binary numbers, Full Adders are the basic building blocks in arithmetic circuits. They find use in processors, calculators and other digital systems that require addition.
• Data Encryption : Full Adders play a part in cryptographic algorithms and data encryption techniques where binary addition operations are involved in the encryption and decryption processes.
• Address Generation : To access specific memory locations or devices based on the calculated addresses, Full Adders are utilized in memory systems and microcontrollers for address generation purposes.

Conclusions

The presented code of verilog indicates a Full add that has two input bits and one carry input, which then produces sum and carry output bits. The information contained in this code is used to find the sum and carry from inputs A, B as well as Cin. It is worth noting that this module can be used to perform addition operations on digital circuits.