GATE | CS | 2022 | COA | Cache Memory | Question 25

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Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?

Each cache block in WB and WT has a dirty bit

Every write hit in WB leads to a data transfer from cache to main memory. 

Eviction of a block from WT will not lead to data transfer from cache to main memory

A read miss in WB will never lead to eviction of a dirty block from WB

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Computer Organization and Architecture,GATE CS 2022,Computer Organization and Architecture GATE CS PYQs,Cache memory PYQ QUIZ GATE CS
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