- Interview Prep
- Tutorials
- Tracks
Cache and main memory
Question 1
A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is
11
14
16
27
Question 2
Consider the data given in previous question. The size of the cache tag directory is
160 Kbits
136 bits
40 Kbits
32 bits
Question 3
In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?
Smaller block size incurs lower cache miss penalty
Smaller block size implies better spatial locality
Smaller block size implies smaller cache tag
Smaller block size implies lower cache hit time
Question 4
In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from.
(j mod v) * k to (j mod v) * k + (k-1)
(j mod v) to (j mod v) + (k-1)
(j mod k) to (j mod k) + (v-1)
(j mod k) * v to (j mod k) * v + (v-1)
Question 5
A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is
4
5
6
7
Question 6
An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following. 1 Valid bit 1 Modified bit As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?
4864 bits
6144 bits
6656 bits
5376 bits
Question 7
A main memory unit with a capacity of 4 megabytes is built using 1M × 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is:-
A.100 nanoseconds
B.100×210 nanoseconds
C.100×220 nanoseconds
D.3200×220 nanoseconds
A
B
C
D
Question 8
A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively.
When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?
2 nanoseconds
20 nanoseconds
22 nanoseconds
88 nanoseconds
Question 9
Consider the data from above question. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?
222 nanoseconds
888 nanoseconds
902 nanoseconds
968 nanoseconds
Question 10
How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
8
32
64
128
There are 60 questions to complete.