Zero ASIC releases Platypus eFPGA upgrade with BRAM and DSP blocks

The FM-S18 is an FPGA Mezzanine Card (FMC) module that provides up to eight SFP/SFP+ module interfaces directly into Multi-Gigabit Transceivers (MGTs) of an AMD FPGA. The FM-S18 supports the industry standard Small Form-factor Pluggable (SFP/SFP+) transceiver module interface. More details: https://lnkd.in/gHdtrCwd

Packet Architects builds high-performance Ethernet switch and router IP cores, generated by our in-house FlexSwitch toolchain for FPGA or ASIC designs. The generator produces a complete package: datasheet, C-API, and synthesizable system verilog for the IP core. Our L2/L3 switch/router core, for example: - Delivers full wire-speed on all ports - Uses a shared buffer memory architecture optimized for simultaneous high-throughput switching - Provides multiple egress queues per port (with a multi-level scheduler), enabling rich QoS and traffic shaping policies  - Provides extensize switching , routing and tunneling

🚀 Predicting the future — just another day in processor design! Wrapped up an exciting SystemVerilog project: a 2-way set-associative Branch Target Buffer (BTB) powering smarter RISC-V branch prediction. 💡 What it does: predicts branch directions, updates targets, and keeps the pipeline running smoothly — all thanks to a 2-bit dynamic predictor and an LRU replacement policy. 📌 Highlights: • Simulated and synthesised on Artix-7 FPGA • Verified branch hits, mispredictions, and target updates through waveform analysis • Optimised pipeline efficiency and resource usage Check out the waveform screenshot — you can see the BTB in action, predicting branches and updating targets in real time! 🔗 See the full project: https://lnkd.in/dDtpzXQ7 #FPGA #SystemVerilog #RISC_V #BranchPrediction #HardwareDesign #DigitalDesign #Vivado

What are the precautions and techniques for FPGA pin configuration? This is a critical topic in FPGA design. Improper pin configuration is a leading cause of board bring-up failures. Here is a comprehensive guide to the precautions and techniques for FPGA pin configuration. Here’s a practical, engineer-friendly guide you can drop into your pin-planning flow. View more details, please click: https://lnkd.in/edr5jqBx #FPGA #pinconfiguration #Xilinx7Series #SoC #Zynq #UltraScale #XilinxFPGA #IntelFPGA

𝙈𝙖𝙨𝙩𝙚𝙧 𝘼𝙓𝙄 𝙩𝙝𝙚 𝙍𝙞𝙜𝙝𝙩 𝙒𝙖𝙮 — 𝙁𝙧𝙤𝙢 𝙎𝙩𝙧𝙚𝙖𝙢 𝙩𝙤 𝙄𝙣𝙩𝙚𝙧𝙘𝙤𝙣𝙣𝙚𝙘𝙩 If you’re into FPGA Design, SoC Architecture, or Verification, mastering the AMBA AXI protocol is a must. This roadmap breaks down the complete learning journey from basics to expert level 👇 🧩 𝙎𝙩𝙚𝙥 1: 𝙎𝙩𝙖𝙧𝙩 𝙎𝙞𝙢𝙥𝙡𝙚 — 𝘼𝙓𝙄 𝙎𝙩𝙧𝙚𝙖𝙢 🔹Understand point-to-point data transfers. 🔹Learn how to build an AXI Stream interface and AXIS Arbiter. ⚙️ 𝙎𝙩𝙚𝙥 2: 𝙈𝙤𝙫𝙚 𝙩𝙤 𝘼𝙓𝙄-𝙇𝙞𝙩𝙚 🔹Explore memory-mapped interfaces for simple control/status operations. 🔹Build AXI GPIO and AXI-Lite Interconnects. 🧠 𝙎𝙩𝙚𝙥 3: 𝘿𝙞𝙫𝙚 𝙞𝙣𝙩𝙤 𝘼𝙓𝙄-𝙁𝙪𝙡𝙡 🔹Design AXI Full Slaves for high-performance data transactions. 🔹Learn how to manage burst transfers and handshaking. 🔗 𝙎𝙩𝙚𝙥 4: 𝙈𝙖𝙨𝙩𝙚𝙧 𝙄𝙣𝙩𝙚𝙧𝙘𝙤𝙣𝙣𝙚𝙘𝙩𝙨 🔹Build AXI Full Interconnects and Crossbars to connect multiple masters/slaves efficiently. 🏁 𝙎𝙩𝙚𝙥 5: 𝙐𝙣𝙙𝙚𝙧𝙨𝙩𝙖𝙣𝙙 𝘼𝙙𝙫𝙖𝙣𝙘𝙚𝙙 𝙁𝙚𝙖𝙩𝙪𝙧𝙚𝙨 🔹Learn about credit-based interfaces, QoS, and performance optimization. 💡 Whether you’re designing IPs, verifying SoCs, or exploring FPGA-based systems — mastering the AXI protocol opens doors to high-speed, scalable, and industry-ready designs. PRSsemicon Technologies (A PRSGroup company) Spec2Chips Semiconductor (A PRSGroup company) #AMBA #AXI #FPGA #SoCDesign #VLSI #RTLDesign #Verification #ASICDesign #Semiconductors #AXIInterconnect #FPGAEngineer

🔹 Day 32 of #50DaysOfRTL — Fractional Clock Divider using Vivado Clocking Wizard ⏱️ Today’s focus was on Fractional Clock Dividers, a crucial component in achieving precise frequency synthesis and phase alignment in digital systems. Using Xilinx Vivado’s Clocking Wizard IP, I: Configured MMCM/PLL parameters for custom fractional frequency generation Analyzed the relationship between input and output clock domains Integrated the generated clk_wiz_0 module within a top-level RTL design Developed and verified a SystemVerilog testbench to validate correct frequency division and duty-cycle performance This task strengthened my understanding of clock management, jitter control, and synchronization in FPGA design — key elements for high-performance SoC and ASIC implementations. #RTLDesign #VLSI #FPGA #Vivado #ClockDesign #MMCM #PLL #DigitalElectronics #TimingAnalysis #Verification #SystemVerilog #Day32

The MicroBlaze V is one of the best things you can drop into you FPGA, in place of complex state machines etc. It really does make the design and verification easier. You might think it will take a lot of logic but this week I am looking at the different configurations and RISC-V ISA options to determine the foot print impacts. https://lnkd.in/eWnGmdqF

📡 QAM Communication IP — Flexible Modulation at Scale Quadrature Amplitude Modulation remains vital in modern comms. 🌐 This QAM IP offers: 🔸 Scalable modulation schemes 🔸 Reliable performance for broadband systems 🔸 Simplified integration with FPGA platforms An essential building block for advanced wireless designs. #QAM #WirelessCommunication #FPGA #SignalProcessing #ModulationTechniques #TelecomEngineering #SystemDesign

🔍 𝗛𝗼𝘄 𝘁𝗼 𝗖𝗵𝗼𝗼𝘀𝗲 𝘁𝗵𝗲 𝗥𝗶𝗴𝗵𝘁 𝗙𝗹𝗮𝘀𝗵 𝗳𝗼𝗿 𝗙𝗣𝗚𝗔 𝗖𝗼𝗻𝗳𝗶𝗴𝘂𝗿𝗮𝘁𝗶𝗼𝗻 ? Most FPGA bring-up delays come from one small yet critical choice, nothing but the 𝗰𝗼𝗻𝗳𝗶𝗴𝘂𝗿𝗮𝘁𝗶𝗼𝗻 𝗳𝗹𝗮𝘀𝗵 𝗳𝗼𝗿 𝗙𝗣𝗚𝗔 𝗯𝗼𝗼𝘁𝗶𝗻𝗴. Here’s a simple way to make that choice confidently. 1️⃣ 𝘝𝘦𝘯𝘥𝘰𝘳 𝘊𝘰𝘮𝘱𝘢𝘵𝘪𝘣𝘪𝘭𝘪𝘵𝘺: Check if your FPGA supports SPI, QSPI, or Parallel flash. Refer to vendor-supported lists (UG908, AN370, etc.). 2️⃣ 𝘊𝘢𝘱𝘢𝘤𝘪𝘵𝘺:  Must fit the entire bitstream with ~30% margin for safety or dual images. 3️⃣ 𝘚𝘱𝘦𝘦𝘥 & 𝘔𝘰𝘥𝘦:  Go for SPI modes(x1/x2/x4) or Fast mode configuration. 4️⃣ 𝘝𝘰𝘭𝘵𝘢𝘨𝘦 𝘔𝘢𝘵𝘤𝘩: Ensure correct I/O voltage (1.8V or 3.3V) and footprint. 5️⃣ 𝘈𝘷𝘢𝘪𝘭𝘢𝘣𝘪𝘭𝘪𝘵𝘺: Prefer stable vendors and parts with long-term supply. Avoid EOL or unlisted variants. 💡 A well-chosen flash ensures smoother configuration and fewer surprises in the lab. #FPGA #TheFPGAMan #Vivado #FPGAConfiguration #HardwareDesign #AMD #Altera #Latice #microchip

Chip down design or SOM for your next FPGA development? It can be an interesting discussion. Tomas Chester's looks at the different strategies which can be used for chip down and SoM based approaches in his FPGA Horizons article. https://lnkd.in/e4pXnNde