DAMO院 and Arteris collaborate on RISC-V SoC design

AAEON PICO-ARU4: 15th Gen Intel Core Ultra 2 Pico-ITX SBC The AAEON PICO-ARU4 is a powerful Pico-ITX single board computer (SBC) built on the 15th Gen Intel Core Ultra (Arrow Lake) Series 2 SoC. Compact yet highly capable, this board delivers advanced performance, versatile connectivity, and long-life reliability, making it an ideal solution for industrial and embedded computing applications. https://buff.ly/qdkkUCL #EmbeddedSystems #IndustrialComputing #OEMDesign #SystemIntegration #UKManufacturing #CustomHardware #BVM

The StreamDSP sFPDP-Gen3 (VITA 17.3) IP core now supports the Lattice Avant G/X families! The Lattice Avant mid-range FPGA family supports transceiver link speeds up to 25G. Visit Lattice for more details on the Avant family! Lattice Semiconductor

🤝 ECOSYSTEM NEWS: Arteris and Alibaba 达摩院 Extend Partnership to Accelerate High-Performance RISC-V SoC Designs. We are deepening the collaboration to accelerate high-performance RISC-V International computing across AI, server, and automotive applications. The partnership combines Arteris’ Ncore cache coherent and FlexNoC non-coherent interconnect IPs with XuanTie’s high-performance CPU cores delivering pre-validated, ready-to-use SoC solutions that shorten development time and boost performance. 🎙 Jing Yang, Vice President of RISC-V at DAMO Academy: “Through our collaboration with Arteris, we have completed a seamless integration between multiple high-performance CPUs — including the newly released C930 — and Arteris’ Ncore interconnect IP. This ‘out-of-the-box’ compatibility accelerates the entire process from architecture design to prototype verification, allowing our customers to focus on innovation and differentiation.” 🔗 Learn more in the press release: https://hubs.ly/Q03PvLVS0 #RISCVEverywhere #SoC #AI #semiconductors #Arteris #innovation #NoC #chiplets

In the evolving landscape of edge computing for enterprise environments, the Minisforum MS-R1 introduces a compact Arm-based solution with a 12-core Cix CD8180 SoC, 64GB RAM, dual 10Gbps NICs, and PCIe expansion. This hardware promises enhanced productivity in homelab and small-scale AI deployments, potentially reducing infrastructure costs by up to 30% through efficient Arm architecture. However, challenges such as high idle power consumption and variable performance benchmarks highlight areas for improvement before it can compete with established Arm platforms like Apple's M1. For IT leaders exploring Arm for RAG systems and AI agents, this device offers valuable lessons in balancing...

Introducing Fabric100 — A High-Speed OpenVPX Fabric for Mission-Critical Systems In today’s defence and industrial environments, data must flow immediately, reliably and at high speed. Fabric100 from Curtiss-Wright Defence Solutions offers a complete 100 Gigabit Ethernet fabric ecosystem tailored for rugged OpenVPX deployments. With true 100 GbE backplane connectivity, full alignment with MOSA and the SOSA Technical Standard, and a portfolio spanning switches, GPUs, processor modules and I/O, Fabric100 gives systems engineers a ready-made high-bandwidth backbone. Ideal for sensor-fusion, EW, ISR and heavy-data collection nodes, this platform enables high-performance embedded systems to operate at the speed of relevance while reducing integration risk and enhancing future-proofing. https://lnkd.in/dWdNbf5e

Microchip Technology Inc. has a great IP under "PolarFire Family Memory Controller" named "Octal DDR PHY" for x8 memory interfaces such as xSPI, HyperBUS and ONFI flash memories. It's HSIO also support 600 MHz (1200 MTPS with DDR). So, one might think it is possible to use this IP to interface an ONFI 4.x flash memory supports transfer rate of 1200 MTPS. But, then check the IP document and you will find this: "The Octal DDR PHY-Only solution supports up to 250 MHz operations and is available in GPIO and HSIO banks". Another option is to try to use PF_IOD_Generic_*X. But it's intend is to use RX only or TX only. And if you want to tweak and try to change I/O buffers with BIBUF on the netlist you got error also. I wonder if it's possible to connect ONFI 4.x flash memory to Polarfire? #FPGA #VHDL #MEMORY #SoC #Verilog

Socionext Inc. introduces Flexlets, a configurable chiplet ecosystem advancing SoC performance, scalability, flexibility, and interoperability. #chipletecosystem #configurablechiplets #Flexlets #heterogeneousintegration #HighPerformanceComputing #News #PCIeGen7 #SemiconductorInnovation #SoCDesign #socionext #UCIe

In his latest 'Diaries of a Network Architect' (DNA) blog, Starfish CEO Stephen Hampton takes a close look at some of the NVIDIA hardware portfolio: ✅ NVLink ✅ NVSwitch ✅ ConnectX ✅ BlueField ✅ QuantumX ✅ SpectrumX Read the full blog here: https://lnkd.in/ejFqHu26 Follow us to be notified of an upcoming deep dive on some of the solutions and their alternatives in coming weeks. #nvidia #hardware #networking #networkarchitecture #networkinfrastructure

💬 Communication is key - even for a processor! Built a complete RISCV System-on-Chip (SoC), entirely from scratch. 💡 What started as a 5-stage pipelined RISC-V RV32IM core evolved into a modular, scalable SoC powered by an AXI4-Lite interconnect enabling seamless communication between the CPU, memory, and peripherals. 📌 Key Highlights: 🔹 AXI4-Lite Interconnect for memory-mapped I/O 🔹 Branch Target Buffer: Cuts branch penalties by ~40% 🔹 Hazard & Forwarding Units for smooth pipelining 🔹 Hardware M-unit: ~21× faster multiply, ~9× faster divide 🔹 Synthesized on Nexys A7 @ 75 MHz This project taught me how to take a RISC-V core from standalone to fully integrated, bridging RTL design, on-chip communication, and real-world hardware. It’s one thing to design a CPU. It’s another to make it communicate. 🧠💻 🔗 Check it out: https://lnkd.in/dzhnEM6J #RISCV #SoCDesign #FPGA #AXI4Lite #DigitalDesign #ProcessorDesig #AMBA #RTLDesign #HardwareEngineering

MTrion 🚀 System on Modules support the Trion® FPGA family by Efinix, Inc. and are the ideal solution to get FPGA projects quickly to market. The Mtrion SoMs support on-board DDR3 RAM, expose 🔧 the MIPI-CSI and LVDS signals to the baseboard, they are the ideal fit for digital-logic as well as RISC-V 💪 based softcore implementations. Trion products are designed into a broad range of applications in many diverse markets 🎯. The Trion family of FPGAs is supported in customer designs with very good longevity, so are the MTrion SoMs. #fpga #efinix #trion #RISCV