Why #UVM struggled with backward compatibility

Not all 5G RedCap modules are equal - and your design needs to hit performance, compliance, and cost targets. Our article walks through early RedCap hardware on the market, what to look for, and how to select modules that meet certification standards while simplifying your design process. As an engineer, understanding RedCap’s evolving module landscape helps you design smarter, faster, and more cost-effectively. • Compliance with future 3GPP releases • Hardware simplification = faster time to market • RedCap modules built for embedded/industrial use Accelerate design cycles by getting familiar with RedCap-ready modules and their key differences: https://bit.ly/3Usm4oC #5GModules #WirelessIntegration #EmbeddedDesign #RedCap

We’re happy to deepen our collaboration with 达摩院 advancing high-performance RISC-V International SoC design and innovation 🤝 Jing Yang, VP of RISC-V at DAMO Academy, shared: “Through our collaboration with Arteris, we have completed a seamless integration between multiple high-performance CPUs — including the newly released C930 — and Arteris’ Ncore interconnect IP. This ‘out-of-the-box’ compatibility accelerates the entire process from architecture design to prototype verification, allowing our customers to focus on innovation and differentiation.” Learn more: https://hubs.ly/Q03PvLVS0 #RISCVEverywhere

The RT-Thread community developer built a system that can make a ping-pong ball float in a wind tunnel using RT-Thread and NXP Semiconductors FRDM-MCXA156. Simple, real-time control and remote monitoring are at the core of this project! 🎥 Check it out:https://lnkd.in/gkNtu8RM 🔧 Tutorial coming soon! #TechDemo #EmbeddedSystems #RTThread #NXP

PCI-SIG recently approved iPasslabs as an official Authorized Test Lab (ATL), the first PCI-SIG ATL in the APAC region. Eric Shen (iPasslabs) walks through the specific tests offered as an ATL for companies wanting to reach PCIe specification compliance, how this supports member testing efforts in the APAC region and more in the  blog on the PCI-SIG website. Learn more about the growing PCI-SIG ATL program > https://bit.ly/3KgRa0w #PCISIG #PCIe #optical #CopprLink

PCI-SIG member companies can contribute to the development of PCIe technology and participate in Compliance Workshops. Members also receive direct access to PCIe technical support and more.   Find the full list of membership benefits and instructions on how to become a member on the PCI-SIG website > https://bit.ly/3Tffa3l   #PCISIG #PCIe #optical #CopprLink

The maturity of the Risc V standard is happening - Tenstorrent Ascalon X is more performant than the Arm neoverse family of processors (neoverse is used in Nvidia Grace Blackwell) I’m not surprised- Jim Keller has been behind major CPU chips over 30 years and so it’s not that Risc V is not a good instruction set, it’s that it needs belief in open source and commitment to make it happen. Whilst companies still will need to license platforms like Ascalon, the open source framework means that companies don’t have to rewrite their compiler and software stack should they choose to switch chips. It simply means that there is more room for innovation and less for monopolistic behavior. Watch th video for the full briefing. https://lnkd.in/giPazEXk

New IP: LPC Verification IP from Truechip https://lnkd.in/eUtFp6u2 The LPC Verification IP provides an effective & efficient way to verify the LPC components of an IP or SoC. The LPC VIP is fully compliant with LPC Specification version 1.1 The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time. Learn more at https://lnkd.in/eUtFp6u2 #semiIP #IPcores #semiconductor #semiEDA

As SoCs and chiplets grow more complex, integration speed and consistency are everything. That’s where IP-XACT comes in, a standard that defines IP metadata in a structured, machine-readable format. The result is ✅ Seamless tool interoperability ✅ Consistent hardware/software alignment ✅ Faster, automated integration The latest IP-XACT 2022 extends support across IPs, subsystems, and multi-die systems helping teams design “correct-by-construction” hardware. If you’re an SoC architect building or integrating IPs, this article by Insaf Meliane for Electronic Design will certainly be of interest ⤵️

As SoCs and chiplets become more complex, integration speed and consistency are critical. That’s where IP-XACT steps in defining IP metadata in a structured, machine-readable format that unifies hardware and software views. The below article is an insightful read for SoC architects and integration engineers for a clear breakdown of how structured metadata accelerates innovation 👇

Most teams focus on throughput and CTS compliance—but what about Quality of Service? QoS features in UniPro v1.8 and v2.0 are designed to optimize link reliability, latency, and adaptive performance in real-world conditions. Yet they’re often overlooked in validation workflows. 👉 Click https://lcry.us/493CiNp to learn why QoS matters for next-gen UFS deployments—and how Teledyne LeCroy’s Eclipse M52 can leverage the Stimulus Editor to create custom QoS and other tests. #TeledyneLeCroy #UFS #UniPro #QoS #ProtocolAnalysis #EmbeddedSystems #StorageValidation