Serious about Production, Ever Been in Fabs?
The added value of hands-on product engineering and manufacturing know-how
The roots of a bold industry quote
“Now hear me and hear me well. Real [guys]have Fabs!”. The title of this blog comes from this reported memorable quote by semiconductor icon and former AMD CEO, Jerry Sanders.
Three decades later, such a quote may give us pause: the fabless model has unquestionably triumphed, and fortunately, our semiconductor industry is now home to leading women executives. But Sanders’ controversial quote still resonates — not for what it says about owning fabs for leadership, but for what it says about the value of hands-on experience in semiconductor manufacturing and device engineering in a world where supply chain services are becoming ubiquitous. It underscores that actual semiconductor manufacturing experience still makes a difference today when producing and releasing ASICs into foundries.
What tapeout really means in semiconductor development.
Every industry has a critical go/no-go gating moment. In semiconductors, it’s the tapeout: the point at which all the ASIC silicon design and verification work is frozen, production mask making is triggered, and the wafer manufacturing process begins. This is when the rubber hits the road.
Tapeout isn’t just about passing thorough automated EDA checks. It means that silicon ASIC must hold up under real-world manufacturing variations, yield conditions, and lifetime reliability, and that any design rule waiver decisions must be made diligently. Nothing’s perfect, in the real world, and there are always trade-offs to make. And this is where hands-on fab knowledge shows its worth.
Why Presto’s approach to tapeout is different
Plenty of companies can support ASIC tapeouts. But few offer the depth of product engineering expertise you get from people who have tuned process knobs on fab tools, optimized lithography FEM (Focus Exposure Matrix) for defectivity reduction, or solved yield-limiting parasitics through layout changes. At Presto, our team doesn’t just run EDA sign-offs - we go further:
It’s not about being expert on the tools — it’s about manufacturing experience
A successful tapeout isn’t just about being experts with complex software. It’s about understanding the why and how of each decision and trade-off building something manufacturable, yield-optimized, and resilient.
If automated software verification is key, knowing which configuration file, or deck rules and switches to activate in the command line or graphical interface is not enough. It does not eliminate blind spots, and must be under supervision based on empirical and hands-on expertise. Our experts apply decades of hands-on experience in fab device engineering to prevent issues that simulation alone can’t fully anticipate - or can create false error flag.
I still painfully recall how a very elegant PLL design can be ruined because of a theoretical decision on how transistors are built - even in mature technologies. The contact etch stop layer – a layer used to stop selectively contact chemical etching – can, depending on material composition, cause excessive trapping leakage current and result in capacitor-based VCO undesirable drift and phase noise. The trapping parasitic current is generally conditioned by the layout patterns and distance to all contact on capacitors, or transistors. Such things were not typically modeled in SPICE device libraries, and still are not today in most mature technologies. Designer can indeed simulate this effect but might need to know how to gage the layout design. This is where the EDA software gets back in play but needs the right feeding information. This is beyond the standard foundry PDK, even with Design For Manufacturing (meant for random defectivity reduction). Guiding designers on how to take all this into account is important for a successful tapeout.
Another example could be the design of a higher sensitivity sensor by both adjusting layer shape and requesting to the foundry a specific implant angle for the selected process route.
In a word Presto doesn’t suggest checklist macros based on datasheets, or listing to fill out as-is. We have experienced and skilled former wafer fab manufacturing engineers in our Team who developed embedded flash processes in wafer fab, participated in fab SPICE model creation, and have navigated a variety of unique situations, enabling our customers to benefit from hard-won experience.
Hundreds of tapeouts and a reputation built on reliability and people
Presto Engineering has successfully brought hundreds of ASICs into volume production. From 250nm to FinFET, our teams support customers through every phase - from tapeout to ramp-up - and beyond.
We’re not just a service provider. We’re your partner in turning your design into first-time-right silicon, built to last, with a supply chain you can truly rely on.
As a service company the value lies in our people, their expertise, and our core values.
I know many will argue and talk about AI and how it can streamline these checks. We will come back to that—stay tuned!
But to have an artificially intelligent support system, don’t you need a truly experienced model to train it?
➡️ Curious how this translates to your product? Explore our semiconductor manufacturing services: https://www.presto-eng.com/production