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Experiment-1: Aim: Program of VHDL To Study The Not Gate

The document contains 17 experiments on digital logic circuits and their implementation in VHDL including gates, half adder, full adder, comparator, multiplexer, priority encoder, gray-binary converter, and shift registers. Each experiment provides the aim, VHDL code using either behavioral or structural modeling, and output waveforms for the designed circuit.

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81 views75 pages

Experiment-1: Aim: Program of VHDL To Study The Not Gate

The document contains 17 experiments on digital logic circuits and their implementation in VHDL including gates, half adder, full adder, comparator, multiplexer, priority encoder, gray-binary converter, and shift registers. Each experiment provides the aim, VHDL code using either behavioral or structural modeling, and output waveforms for the designed circuit.

Uploaded by

jaigodara
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT-1

AIM: PROGRAM OF VHDL TO STUDY THE NOT GATE AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all;

entity \NOT\ is port( A : in STD_LOGIC; B : out STD_LOGIC ); end \NOT\;

architecture \BODY\ of \NOT\ is begin B<=NOT A; end \BODY\;

EXPERIMENT-2
AIM: PROGRAM OF VHDL TO STUDY THE VARIOUS GATES AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all;

entity GATES is port( A : in STD_LOGIC; B : in STD_LOGIC; C: out std_LOGIC ); end GATES;

architecture BODY of GATES is begin CAND<=A AND B AND C; COR<=A OR B OR C; CXOR<=A XOR B XOR C; CNAND<=A NAND B NAND C; CNOR<=A NOR B NOR C; CXNOR<=A XNOR B XNOR C; end BODY;

EXPERIMENT-3
AIM: PROGRAM OF VHDL TO STUDY HALF ADDER AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.)

library IEEE; use IEEE.STD_LOGIC_1164.all; entity half adder is port( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC end half adder; architecture body of half adder is begin Sum<=A XOR B; Carry<=A AND B; end body; );

EXPERIMENT NO-4
AIM: PROGRAM OF VHDL TO STUDY FULL ADDER AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity fulladdr is port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC ); end fulladdr; architecture fulladdr of fulladdr is begin sum<=a xor b xor c; carry<=(a and b)or(b and c)or(c and a); end fulladdr; Output waveform:

EXPERIMENT-5
AIM: PROGRAM OF VHDL TO STUDY HALF ADDER WITH BEHAVIOUR MODELLING AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux is port( a : in BIT_VECTOR(0 to 7); s : in BIT_VECTOR(0 to 2); o : out BIT); end mux; architecture muxbody of mux is begin process(s,a) begin case s is when"000"=>o<=a(0); when"001"=>o<=a(1); when"010"=> o <=a(2); when"011"=> o <=a(3); when"100"=> o <=a(4); when"101"=> o <=a(5); when"110"=> o <=a(6);

when"111"=> o <=a(7); when others => o <='0'; end case; end process; end muxbody; Output waveform:

EXPERIMENT-6
AIM: DESIGN VHDL PROGRAM FOR A 4-BIT COMPARATOR USING BEHAVIOUR MODELING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.)

library IEEE; use IEEE.STD_LOGIC_1164.all; entity comparator_entity is port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); abc ,def,ghi: out STD_LOGIC ); end comparator_entity; architecture comparator_architecture of comparator_entity is begin abc<='1'when (A)<(B) else '0'; def<='1'when (A)=(B) else '0'; ghi<='1'when (A)>(B) else '0'; end comparator_architecture;

Output Waveform:

EXPERIMENT-7
AIM: WRITE a VHDL PROGRAM FOR PRIORITY ENCODER. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all;

entity encoder is port( i:in std_logic_vector(7 downto 0); o:out std_logic_vector(2 downto 0) ); end encoder; architecture encoder of encoder is begin process(i) begin if (i(7)='1') then o<="111"; elsif i(6)='1' then o<="110"; elsif i(5)='1' then o<="101"; elsif i(4)='1' then o<="100"; elsif i(3)='1' then o<="011"; elsif i(2)='1' then o<="010";

elsif i(1)='1' then o<="001"; else o<="000"; end if; end process; end encoder;

Output:- Waveform:

EXPERIMENT-8
AIM: WRITE a VHDL PROGRAM for MOD 10 COUNTER. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dec_coun is port (clk:in bit; clr: in std_logic; o: out std_logic_vector(3 downto 0)); end dec_coun; architecture dec_beh of dec_coun is signal temp : std_logic_vector(3 downto 0); begin process(clk) begin if clk='1'then if clr='1' then temp<="0000"; elsif temp="1001" then temp<="0000"; else temp<=temp+1;

end if; end if; end process; O<=temp; end dec_beh; Output:- Waveform:

EXPERIMENT-9
AIM: WRITE a VHDL PROGRAM FOR PISO USING BEHAVIOUR MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.)

library IEEE; use IEEE.STD_LOGIC_1164.all; entity piso_entity is port( PI : in STD_LOGIC_VECTOR(3 downto 0); clk : in STD_LOGIC; load : in STD_LOGIC; set : in STD_LOGIC; so : out STD_LOGIC ); end piso_entity; architecture piso_architecture of piso_entity is signal temp_so:std_logic_vector(3 downto 0); begin process(clk) begin if rising_edge(clk) then

if set='1' then temp_so<="1111"; elsif load='1' then temp_so<=PI; else temp_so<='0' & temp_so(3 downto 1); end if; end if; end process; so<=temp_so(0); end piso_architecture; Output:- Waveform:

EXPERIMENT-10
AIM: WRITE a VHDL PROGRAM TO IMPLEMENT AN SIPO SHIFT REGISTER. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use ieee.std_logic_1164.all; entity sipo is port(si,clk:in bit; po:out bit_vector(3 downto 0)); end entity; architecture sipo_beh of sipo is signal temp:bit_vector(3 downto 0); begin process(clk) begin if clk='1' and(not clk'stable) then temp<="0000"; temp<=si & temp(3 downto 1); end if; end process; po<=temp; end architecture;

Output:- Waveform:

EXPERIMENT NO.-11 AIM: PROGRAM TO IMPLIMENT GRAY TO BINARY CONVERTER USING BEHAVIOURIAL MODELLING AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all;

entity \grey binary\ is port( gr : in STD_LOGIC_VECTOR(3 downto 0); bin : out STD_LOGIC_VECTOR(3 downto 0) ); end \grey binary\;

architecture \grey binary\ of \grey binary\ is begin process(gr) begin bin(3)<=gr(3); bin(2)<=gr(3) xor gr(2); bin(1)<=gr(3) xor gr(2) xor gr(1); bin(0)<=gr(3) xor gr(2) xor gr(1) xor gr(0); end process; end \grey binary\;

O/P waveform:

EXPERIMENT-12
AIM: WRITE a VHDL PROGRAM TO IMPLEMENT BINARY TO GRAY CONVERTER. AZIZ PRADHAN 67 M.TECH 1st SEM (E.C.E.) library ieee; use ieee.std_logic_1164.all; entity b2g is port(b:in std_logic_vector(3 downto 0); g:out std_logic_vector(3 downto 0)); end b2g; architecture b2g_beh of b2g is begin g(0)<=b(0)xor b(1); g(1)<=b(1)xor b(2); g(2)<=b(2)xor b(3); g(3)<=b(3); end architecture;

Output Waveform:

EXPERIMENT-13
AIM: WRITE a VHDL PROGRAM FOR HALF ADDER WITH STRUCTURAL MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity half_adder_entity is port( a : in bit; b : in bit; o : out bit ; c : out bit); end half_adder_entity; architecture half_adder_architecture of half_adder_entity is component xor2 is port(x,y:in bit; z: out bit); end component; component and2 is port(p,q:in bit; r: out bit); end component; begin x1: xor2 port map(a,b,o); a1: and2 port map(a,b,c);

end half_adder_architecture; library ieee; use ieee.std_logic_1164.all; entity xor2 is port(a,b:in bit; o: out bit); end xor2; architecture xor2 of xor2 is begin o<=a xor b; end xor2;

library ieee; use ieee.std_logic_1164.all; entity and2 is port(a,b:in bit; c: out bit); end and2; architecture and2 of and2 is begin c<=a and b; end and2; OUTPUT WAVEFORM:

EXPERIMENT-14
AIM: PROGRAM OF VHDL TO STUDY THE VARIOUS GATES WITH BEHAVIOUR MODELLING . AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) Library IEEE; use IEEE.STD_LOGIC_1164.all;

entity gates_entity is port( A : in STD_LOGIC; B : in STD_LOGIC; CAND : out STD_LOGIC; COR : out STD_LOGIC; CXOR : out STD_LOGIC; CNAND : out STD_LOGIC; CNOR : out STD_LOGIC; CXNOR : out STD_LOGIC ); end gates_entity; architecture gates_architecture of gates_entity is begin process(A,B) begin

CAND<=A AND B;

COR<=A OR B; CXOR<=A XOR B; CNAND<=A NAND B; CNOR<=A NOR B; CXNOR<=A XNOR B; END PROCESS; end gates_architecture; OUTPUT WAVEFORM:

EXPERIMENT-15
AIM: PROGRAM OF VHDL TO STUDY THE VARIOUS GATES WITH STRUCTRUAL MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity gates_entity is port( a : in bit; b : in bit; cand : out bit; cor : out bit; cxor : out bit; cnand : out bit; cnor : out bit; cxnor : out bit ); end gates_entity; architecture gates_architecture of gates_entity is

component xor2 is port(a1,b1:in bit; o1:out bit);

end component;

component and2 is port(a2,b2:in bit; o2:out bit); end component;

component or2 is port(a3,b3:in bit; o3:out bit); end component;

component nand2 is port(a4,b4:in bit; o4:out bit); end component;

component nor2 is port(a5,b5:in bit; o5:out bit); end component;

component xnor2 is port(a6,b6:in bit; o6:out bit);

end component;

begin c1:xor2 port map(a,b,cxor); c2:and2 port map(a,b,cand); c3:or2 port map(a,b,cor); c4:nand2 port map(a,b,cnand); c5:nor2 port map(a,b,cnor); c6:xnor2 port map(a,b,cxnor); end architecture;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity xor2 is port(a1,b1: in bit; o1:out bit); end xor2 ; architecture xor2 of xor2 is begin o1<=a1 xor b1; end xor2;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity and2 is

port(a2,b2: in bit;

o2:out bit); end and2 ; architecture and2 of and2 is begin o2<=a2 and b2; end and2;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity or2 is port(a3,b3: in bit; o3:out bit); end or2 ; architecture or2 of or2 is begin o3<=a3 or b3; end or2;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity nand2 is port(a4,b4: in bit; o4:out bit);

end nand2 ;

architecture nand2 of nand2 is begin o4<=a4 nand b4; end nand2;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity nor2 is port(a5,b5: in bit; o5:out bit); end nor2 ; architecture nor2 of nor2 is begin o5 <=a5 nor b5; end nor2;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity xnor2 is port(a6,b6: in bit; o6:out bit); end xnor2 ; architecture xnor2 of xnor2 is

begin

o6<=a6 xnor b6; end xnor2;

OUTPUT WAVEFORM:

EXPERIMENT-16
AIM: DESIGN VHDL PROGRAM FOR A 4-BIT COMPARATOR USING BEHAVIOUR MODELING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity comparator_entity is port( A : in STD_LOGIC_VECTOR(3 downto 0); B : in STD_LOGIC_VECTOR(3 downto 0); AIB ,AeB,AgB: out STD_LOGIC ); end comparator_entity; architecture comparator_architecture of comparator_entity is begin process(A,B) begin if(A)<(B)then AIB<='1'; elsif (A)=(B)then AeB<='1'; else AgB<='1'; end if; end process; end comparator_architecture;\

Output Waveform:

EXPERIMENT-17
AIM:PROGRAM OF VHDL TO STUDY MULTIPLEXER WITH STRUCTURAL MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all;

entity mux_entity is port(i0,i1,i2,i3 : in bit; s0,s1 : in bit; o : out bit); end mux_entity; architecture mux_architecture of mux_entity is

component and3 is port(a,b,c:in bit; d:out bit); end component;

component or4 is port(p,q,r,s:in bit; t:out bit); end component;

component inv2 is

port(l:in bit;m:out bit); end component; signal e1,e2,f1,f2,f3,f4 : bit;

begin A1:and3 port map (e1,e2,i0,f1); A2:and3 port map (s0,e2,i1,f2); A3:and3 port map (e1,s1,i2,f3); A4:and3 port map (s1,s0,i3,f4); N1:inv2 port map (s0,e1); N2:inv2 port map (s1,e2); O1:or4 port map (f1,f2,f3,f4,o);

end mux_architecture;

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity and3 is port(a,b,c: in bit; d : out bit); end and3; architecture and3 of and3 is

begin

d<=a and b and c; end and3;

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity or4 is port(p,q,r,s: in bit; t : out bit); end or4; architecture or4 of or4 is begin t<=p or q or r or s; end or4;

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity inv2 is port(l: in bit; m : out bit); end inv2; architecture inv2 of inv2 is

begin

m<= not l; end inv2; Output Waveform:

EXPERIMENT-18
AIM:PROGRAM OF VHDL TO STUDY DEMULTIPLEXER WITH DATAFLOW MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity demux_entity is port( a : in STD_LOGIC; s : in STD_LOGIC_vector(0 TO 1); x,y,z,m : out STD_LOGIC);--_VECTOR(0 TO 3)); end demux_entity; architecture demux_architecture of demux_entity is begin x <= a when s="00"; y <= a when s="01"; z <= a when s="10"; m <= a when s="11"; end demux_architecture;

OUTPUT WAVEFORM:

EXPERIMENT-19
AIM:PROGRAM OF VHDL TO STUDY DEMULTIPLEXER WITH STRUCTURAL MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all;

entity demux_entity is port(i: in bit; s0,s1 : in bit; o0,o1,o2,o3 : out bit); end demux_entity;

architecture demux_architecture of demux_entity is

component and3 is port(a,b,c:in bit; d:out bit); end component;

component inv2 is port(l:in bit;m:out bit); end component;

signal e1,e2: bit; begin A1:and3 port map (e1,e2,i,o0); A2:and3 port map (s0,e2,i,o1); A3:and3 port map (e1,s1,i,o2); A4:and3 port map (s1,s0,i,o3); N1:inv2 port map (s0,e1); N2:inv2 port map (s1,e2);

end demux_architecture;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity and3 is port(a,b,c: in bit; d : out bit); end and3; architecture and3 of and3 is begin d<=a and b and c; end and3;

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity inv2 is port(l: in bit; m : out bit); end inv2; architecture inv2 of inv2 is begin m<= not l; end inv2; Output Waveform:

EXPERIMENT NO-20
AIM: PROGRAM OF VHDL TO STUDY FULL ADDER BEHAVIOUR MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all;

entity FULL_ADDER_ENTITY is port( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; S : out STD_LOGIC; CY : out STD_LOGIC ); end FULL_ADDER_ENTITY; architecture FULL_ADDER_ARCHITECTURE of FULL_ADDER_ENTITY is begin

process(A,B,C) begin S<= A XOR B XOR C; CY<=(A AND B) OR (B AND C) OR (C AND A);

end process;

end FULL_ADDER_ARCHITECTURE;

OUTPUT WAVEFORM:

EXPERIMENT NO-21
AIM: PROGRAM OF VHDL TO STUDY FULL ADDER STRUCTURAL MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity FULL_ADDER_ENTITY is port( a : in bit; b : in bit; c : in bit; sum : out bit; cy : out bit ); end FULL_ADDER_ENTITY; architecture FULL_ADDER_ARCHITECTURE of FULL_ADDER_ENTITY is component xor2 port(a1,a2:in bit; c1: out bit); end component;

component and2 port(b1,b2:in bit; c2: out bit); end component;

component or3 port(d1,d2,d3:in bit; c3: out bit); end component; signal s1,s2,s3,s5: bit;

begin

X1: xor2 port map(a,b,s5); X2: xor2 port map(s5,c,sum); A1: and2 port map(a,b,s1); A2: and2 port map(b,c,s2); A3: and2 port map(a,c,s3); O1: or3 port map(s1,s2,s3,cy); end FULL_ADDER_ARCHITECTURE;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity xor2 is port(a1,a2: in bit; c1:out bit); end xor2; architecture xor2 of xor2 is begin

c1<=a1 xor a2;

end xor2;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity and2 is port(b1,b2: in bit; c2:out bit); end and2; architecture and2 of and2 is begin c2<=b1 and b2; end and2;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity or3 is port(d1,d2,d3: in bit; c3:out bit); end or3; architecture or3 of or3 is begin

c3<=(d1 and d2)or(d2 and d3)or(d3 and d1);

end or3; OUTPUT WAVEFORM:

EXPERIMENT-22
AIM:PROGRAM OF VHDL TO STUDY MULTIPLEXER WITH DATAFLOW. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux_entity is port( i : in STD_LOGIC_vector(0 to 3); s : in STD_LOGIC_vector( 0 to 1); o : out STD_LOGIC ); end mux_entity; architecture mux_architecture of mux_entity is begin with s select o<=i(0)when "00", i(1)when "01", i(2)when "10", i(3)when others; end mux_architecture;

OUTPUT WAVEFORM:

EXPERIMENT-23
AIM: WRITE a VHDL PROGRAM FOR PRIORITY ENCODER WITH DATAFLOW MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all;

entity encoder is port( i:in std_logic_vector(7 downto 0); y:out std_logic_vector(2 downto 0)); end encoder; architecture encoder of encoder is begin y<="111" when i(7)='1' else "110" when i(6)='1' else "101" when i(5)='1' else "100" when i(4)='1' else "011" when i(3)='1' else "010" when i(2)='1' else "001" when i(1)='1' else "000" when i(0)='1'; end encoder;

Output Waveform:

EXPERIMENT NO.-24 AIM: PROGRAM TO IMPLIMENT PRIORITY ENCODER USING STRUCTURAL MODELLING AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity \priority encoder\ is port( d0 : in STD_LOGIC; d1 : in STD_LOGIC; d2 : in STD_LOGIC; d3 : in STD_LOGIC; d4 : in STD_LOGIC; d5 : in STD_LOGIC; d6 : in STD_LOGIC; d7 : in STD_LOGIC; q0 : out STD_LOGIC; q1 : out STD_LOGIC; q2 : out STD_LOGIC ); end \priority encoder\; architecture \priority encoder\ of \priority encoder\ is component or4 is

port(j,k,l,m:std_logic; n:out std_logic); end component; begin o1:or4 port map(d1,d3,d5,d7,q0); o2:or4 port map(d2,d3,d6,d7,q1); o3:or4 port map(d4,d5,d6,d7,q2); end \priority encoder\;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity or4 is port (j,k,l,m:in std_logic; n:out std_logic); end or4; architecture or4 of or4 is begin n<=j or k or l or m; end or4; OUTPUT:-

EXPERIMENT-25
AIM: WRITE a VHDL PROGRAM TO IMPLEMENT BINARY TO GRAY CONVERTER WITH STRUCTURAL . AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library ieee; use ieee.std_logic_1164.all; entity b2g is port(b0,b1,b2,b3:in bit; g0,g1,g2,g3:out bit); end b2g; architecture b2g_beh of b2g is component xor2 port(a1,a2:in bit; c1: out bit); end component;

begin x1:xor2 port map(b3,b2,g2); x2:xor2 port map(b2,b1,g1); x3:xor2 port map(b1,b0,g0); g3<=b3; end architecture;

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity xor2 is port(a1,a2: in bit; c1:out bit); end xor2; architecture xor2 of xor2 is begin c1<=a1 xor a2; end xor2; Output Waveform:

EXPERIMENT-26
AIM: WRITE a VHDL PROGRAM TO IMPLEMENT AN SIPO SHIFT REGISTER USING STRUCTRAL. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; Use IEEE.STD_LOGIC_1164.All; Entity sipo is Port (si: in std_logic; clk: in std_logic; po:buffer std_logic_vector(3 downto 0)); end sipo; architecture structural of sipo is signal d:std_logic_vector(4 downto 0); component d_ff Port (d,clk: in std_logic; q,qbar:buffer std_logic); end component; begin a1:d_ff port map (si, clk, po(3),d(3)); a2:d_ff port map( po(3), clk, po(2),d(2)); a3:d_ff port map (po(2), clk, po(1),d(1)); a4:d_ff port map (po(1), clk, po(0),d(0)); end structural;

library IEEE; Use IEEE.STD_LOGIC_1164.All;

entity d_ff is Port (d : in std_logic; clk : in std_logic; q :buffer std_logic; qbar : buffer std_logic); end d_ff; architecture d_ff of d_ff is begin Process (d,clk) Begin if (clk'event and clk ='1')then if(d='0')then q<='0'; qbar<='1'; else q<='1'; qbar<='0'; end if; else q<=q; qbar<= qbar;

end if; end process; end d_ff;

Output Waveform:

EXPERIMENT-27
AIM: DESIGN VHDL PROGRAM FOR A 3-BIT COMPARATOR USING STRUCTURAL MODELING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity comparator is port(x,y:in std_logic; z:out std_logic ); end comparator ; architecture comparator of comparator is component and2 is port(a1,b1:in std_logic; o1:out std_logic); end component; component or2 is port(a2,b2:in std_logic; o2:out std_logic); end component; component inv2 is port(a3:in std_logic; o3:out std_logic); end component; signal e1,e2,s1,s2: std_logic;

begin I1:inv2 port map(x,e1); I2:inv2 port map(y,e2); A1:and2 port map(x,y,s1); A2:and2 port map(e1,e2,s2); o1:or2 port map(s1,s2,z); end comparator;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity and2 is port(a1,b1: in std_logic; o1:out std_logic); end and2 ; architecture and2 of and2 is begin o1<=a1 and b1; end and2;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity or2 is port(a2,b2: in std_logic; o2:out std_logic);

end or2 ; architecture or2 of or2 is begin o2<=a2 or b2; end or2;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity inv2 is port(a3: in std_logic; o3:out std_logic); end inv2 ; architecture inv2 of inv2 is begin o3<=not a3; end inv2; Output Waveform:

EXPERIMENT-28
AIM: WRITE a VHDL PROGRAM FOR PISO USING DATAFLOW MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all; entity piso_entity is port( clk : in STD_LOGIC; load : in STD_LOGIC; set : in STD_LOGIC; PI : in STD_LOGIC_VECTOR(3 downto 0); so : out STD_LOGIC ); end piso_entity;

architecture piso_architecture of piso_entity is signal temp_so:std_logic_vector(3 downto 0); begin

temp_so<="1111"

when rising_edge(clk)and set='1'else

PI when rising_edge(clk) and load='1' else '0' & temp_so(3 downto 1); so<=temp_so(0);

end piso_architecture; Output Waveform:

EXPERIMENT-29
AIM: WRITE a VHDL PROGRAM FOR PISO USING STRUCTURAL MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; Use IEEE.STD_LOGIC_1164.All;

entity piso is Port (p: in std_logic_vector (3 downto 0); clk: in std_logic; load: in std_logic; so:buffer std_logic); end piso;

architecture structural of piso is

component d_ff is Port (d,clk: in std_logic; q,qbar :buffer std_logic); end component;

component nand2 is

Port (a,b: in std_logic; c: out std_logic); end component;

signal e1,e2,e3,e4,e5,e6,e7,e8,e9,e10: std_logic; signal f1,f2,f3,d0,d1,d2,d3: std_logic; begin n1:nand2 port map (load,load,e1); n2:nand2 port map (e1,p(2),e2); n3:nand2 port map (e2,e3,e4); n4:nand2 port map (load,f3,e3); n5:nand2 port map (p(1),e1,e5); n6:nand2 port map (load,f2,e6); n7:nand2 port map (e5,e6,e7); n8:nand2 port map (p(0),e1,e8); n9:nand2 port map (load,f1,e9); n10:nand2 port map (e8,e9,e10); s1:d_ff port map( p(3),clk,f3,d3); s2:d_ff port map(e4, clk,f2,d2); s3:d_ff port map(e7, clk,f1,d1); s4:d_ff port map(e10, clk, so,d0); end structural;

library IEEE; Use IEEE.STD_LOGIC_1164.All;

entity d_ff is Port (d : in std_logic; clk : in std_logic; q : buffer std_logic; qbar : buffer std_logic); end d_ff; architecture d_ff of d_ff is begin Process (d,clk) Begin if (clk'event and clk ='1')then if(d='0')then q<='0'; qbar<='1'; else q<='1'; qbar<='0'; end if; else q<=q; qbar<= qbar; end if;

end process;

end d_ff;

library IEEE; Use IEEE.STD_LOGIC_1164.All; entity nand2 is Port (a,b: in std_logic; c: out std_logic); end nand2; architecture nand2 of nand2 is begin c<= a nand b; end nand2; Output Waveform:

EXPERIMENT-30
AIM: WRITE a VHDL PROGRAM TO IMPLEMENT AN SIPO SHIFT REGISTER WITH DATAFLOW . AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use ieee.std_logic_1164.all; entity sipo is port(si,clk:in bit; po:out bit_vector(3 downto 0)); end entity;

architecture sipo_beh of sipo is signal temp:bit_vector(3 downto 0); begin temp<="0000" when clk='1' and(not clk'stable) else si & temp(3 downto 1);

po<=temp; end architecture;

Output Waveform:

EXPERIMENT-31
AIM: WRITE a VHDL PROGRAM for MOD 10 COUNTER USING STRUCTURAL MODELLING. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library IEEE; use IEEE.STD_LOGIC_1164.all;

entity decade_entity is port( count : in bit; z : buffer bit_vector(0 to 3) ); end decade_entity;

architecture decade_architecture of decade_entity is component jk_ff is port(j,k,ck:in bit;q,nq:buffer bit); end component; component and2 is port(a,b:in bit;o:out bit); end component; signal s1,s2:bit;

begin

jk1: jk_ff port map('1','1',count,z(0),open); jk2: jk_ff port map('1',s2,z(0),z(1),open); jk3: jk_ff port map('1','1',z(1),z(2),open); jk4: jk_ff port map(s1,'1',z(0),z(3),s2); A1: and2 port map(z(2),z(1),s1); end decade_architecture;

library ieee; use ieee.std_logic_1164.all; entity and2 is port(a,b:in bit;o:out bit); end and2;

architecture and2 of and2 is begin o<=a and b; end and2;

library ieee; use ieee.std_logic_1164.all;

entity jk_ff is

port(j,k,clk:in std_logic;q,nq,z:inout std_logic); end jk_ff;

architecture jk_ff of jk_ff is begin process(clk) begin

if clk='1' then z<=(j and (not q)) or ((not k) and q); q<=z after 5ns; nq<=not z after 5ns; end if; end process; end jk_ff; Output Waveform:

EXPERIMENT-32
AIM: WRITE a VHDL PROGRAM TO IMPLEMENT BINARY TO GRAY CONVERTER WITH DATAFLOW. AZIZ PRADHAN 67 MTECH 1st SEM (E.C.E.) library ieee; use ieee.std_logic_1164.all; entity b2g is port(b:in std_logic_vector(3 downto 0); g:out std_logic_vector(3 downto 0)); end b2g; architecture b2g_beh of b2g is begin process(b) begin g(0)<=b(0)xor b(1); g(1)<=b(1)xor b(2); g(2)<=b(2)xor b(3); g(3)<=b(3); end process; end architecture;

Output Waveform:

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