Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
SPI = Simple, 3 wire, full duplex, synchronous serial data transfer Interfaces to many devices, even many non-SPI peripherals Can be a master or slave interface 4 interface pins: -MOSI master out slave in -MISO master in slave out -SCK serial clock -SS_n slave select 3 registers: -SPCR control register -SPSR status register -SPDR data register
Data is shifted out of the master's (mega128) MOSI pin and in it's MISO pin Data transfer is initiated by simply writing data to the SPI data register. All data movement is coordinated by SCK. Slave select may or may not be used depending on interfacing device. To get input data only you send junk data to SPDR to start the clock.
interrupt enable: if set, interrupt occurs when SPI interrupt flag and global interrupt enable are set spi enable: if set, SPI interface is enabled data order: if set, LSB is transmitted first master/slave select: if set, SPI in master mode clock polarity: '0' SCK low in idle '1' SCK high in idle clock phase: '0' leading edge sample, trailing edge setup '1' leading edge setup, trailing edge sample
(in SPSR)
clock rate
SPI2X SPR1 SPR0 SCLK 0 0 0 fosc/4 0 0 1 fosc/16 0 1 0 fosc/64 0 1 1 fosc/128 1 0 0 fosc/2 1 0 1 fosc/8 1 1 0 fosc/32 1 1 1 fosc/64
reserved bits interrupt flag: set when serial transfer is complete write collision: set if SPDR is written during a receive transfer 2x clock rate: if set, doubles clock rate in master mode
SPDR is a read/write register used for data transfer. Writing SPDR sends data out MOSI. Reading SPDR gets the data that was clocked into MISO.