List of ARM microprocessor cores

List of ARM microprocessor cores

This is a sub-article to ARM architecture. ARM Holdings' microprocessor cores are listed here, sorted by generation release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design.[1] Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM7, ARM9, ARM11, Cortex-M, Cortex-R and Cortex-A device families.

ARM microprocessor cores

Designed by ARM
ARM Family ARM1 ARM2 ARM Architecture ARMv1 ARMv2 ARM Core Feature Cache (I/D), MMU Typical MIPS @ MHz

ARM1 ARM2

First implementation ARMv2 added the MUL (multiply) instruction Integrated MEMC (MMU), Graphics and IO processor. ARMv2a added the SWP and SWPB (swap) instructions. First integrated memory cache.

None None 4 MIPS @ 8MHz 0.33 DMIPS/MHz 7 MIPS @ 12MHz

ARMv2a

ARM250

None, MEMC1a

ARM3

ARMv2a

ARM3

4 KB unified

12 MIPS @ 25MHz 0.50 DMIPS/MHz 10 MIPS @ 12MHz

ARM6

ARMv3

ARM60

ARMv3 first to support 32-bit memory address space (previously 26-bit) As ARM60, cache and coprocessor bus (for FPA10 floating-point unit). As ARM60, cache, no coprocessor bus.

None

ARM600

4 KB unified

28 MIPS @ 33MHz

ARM610

4 KB unified

17 MIPS @ 20MHz 0.65 DMIPS/MHz 40MHz 40MHz 40MHz 0.68 DMIPS/MHz 15 MIPS @ 16.8MHz 63 DMIPS @ 70MHz 36 MIPS @ 40MHz 60 MIPS @ 59.8MHz

ARM7

ARMv3

ARM700 ARM710 ARM710a As ARM700, no coprocessor bus. As ARM710

8 KB unified 8 KB unified 8 KB unified

ARM7TDMI

ARMv4T

ARM7TDMI(-S)

3-stage pipeline, Thumb

none

ARM710T ARM720T

As ARM7TDMI, cache As ARM7TDMI, cache

8 KB unified, MMU 8 KB unified, MMU with Fast Context Switch Extension MPU none

ARM740T ARM7EJ ARMv5TEJ ARM7EJ-S

As ARM7TDMI, cache 5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructions

List of ARM microprocessor cores

[4][]

2
5-stage pipeline, static branch prediction, double-bandwidth memory 5-stage pipeline, Thumb As ARM9TDMI, cache 8 KB unified, MMU 84 MIPS @ 72MHz 1.16 DMIPS/MHz

ARM8

ARMv4

ARM810

ARM9TDMI

ARMv4T

ARM9TDMI ARM920T

none 16 KB/16 KB, MMU with FCSE (Fast Context Switch [5] Extension) 8 KB/8 KB, MMU 4 KB/4 KB, MPU variable, tightly coupled memories, MPU no cache, TCMs 200 MIPS @ 180MHz

ARM922T ARM940T ARM9E ARMv5TE ARM946E-S

As ARM9TDMI, caches As ARM9TDMI, caches Thumb, Enhanced DSP instructions, caches

ARM966E-S

Thumb, Enhanced DSP instructions As ARM966E-S Thumb, Jazelle DBX, Enhanced DSP instructions Clockless processor, as ARM966E-S

ARM968E-S ARMv5TEJ ARM926EJ-S

no cache, TCMs variable, TCMs, MMU no caches, TCMs, MPU 220 MIPS @ 200MHz

ARMv5TE

ARM996HS

ARM10E

ARMv5TE

ARM1020E

6-stage pipeline, Thumb, 32 KB/32 KB, MMU Enhanced DSP instructions, (VFP) As ARM1020E Thumb, Jazelle DBX, Enhanced DSP instructions, (VFP) 8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), Enhanced DSP instructions 8-stage pipeline, SIMD, Thumb-2, (VFP), Enhanced DSP instructions As ARM1136EJ(F)-S 16 KB/16 KB, MMU variable, MMU or MPU variable, MMU 740 @ 532665MHz (i.MX31 SoC), 400528MHz

ARM1022E ARMv5TEJ ARM1026EJ-S

[6]

ARM11

ARMv6

ARM1136J(F)-S

ARMv6T2

ARM1156T2(F)-S

variable, MPU

ARMv6Z

ARM1176JZ(F)-S

variable, MMU + TrustZone

965 DMIPS @ 772MHz, up to 2 600 DMIPS with [7] four processors

ARMv6K

ARM11 MPCore

As ARM1136EJ(F)-S, 14 core SMP

variable, MMU

SecureCore

ARMv6-M ARMv4T ARMv7-M

SC000 SC100 SC300

0.9 DMIPS/MHz

1.25 DMIPS/MHz

List of ARM microprocessor cores

[8]

3
No cache, No TCM, No MPU 0.84 DMIPS/MHz

Cortex-M

ARMv6-M

Cortex-M0

Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, [9] ISB, DSB, DMB), hardware multiply instruction (optional small), optional system timer, optional bit-banding memory Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, [9] ISB, DSB, DMB), hardware multiply instruction (optional small), optional system timer, optional bit-banding memory

Cortex-M0+

[10]

No cache, No TCM, optional MPU with 8 regions

0.93 DMIPS/MHz

Cortex-M1

[11]

Microcontroller profile, Thumb + No cache, 0-1024 KB Thumb-2 subset (BL, MRS, MSR, I-TCM, 0-1024 KB [9] D-TCM, No MPU ISB, DSB, DMB), hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory Microcontroller profile, Thumb / Thumb-2 / DSP / optional FPv4 single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory No cache, No TCM, optional MPU with 8 regions

136 DMIPS @ [12] 170MHz, (0.8 DMIPS/MHz [13] FPGA-dependent)

ARMv7-M

Cortex-M3

[14]

1.25 DMIPS/MHz

ARMv7E-M

Cortex-M4

[15]

No cache, No TCM, optional MPU with 8 regions

1.25 DMIPS/MHz

List of ARM microprocessor cores

[16]

4
Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic 0-64 KB / 0-64 KB, 0-2 of 0-8 MB TCM, opt MPU with 8/12 regions

Cortex-R

ARMv7-R

Cortex-R4

Cortex-R5 [17] (MPCore)

0-64 KB / 0-64 KB, Real-time profile, Thumb / 0-2 of 0-8 MB TCM, Thumb-2 / DSP / optional VFPv3 opt MPU with 12/16 FPU and precision, hardware regions multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port [18] (ACP) 0-64 KB / 0-64 KB, ? Real-time profile, Thumb / of 0-128 KB TCM, Thumb-2 / DSP / optional VFPv3 opt MPU with 16 FPU and precision, hardware regions multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency [18] peripheral port (LLPP), ACP

Cortex-R7 [19] (MPCore)

List of ARM microprocessor cores

[20]

5
Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 14 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 4-64 KB / 4-64 KB L1, MMU + TrustZone 1.57 DMIPS / MHz per core

Cortex-A

ARMv7-A

Cortex-A5

Cortex-A7 MPCore Application profile, ARM / Thumb 32 KB / 32 KB L1, [21] 0-4 MB L2, L1 & L2 / Thumb-2 / DSP / VFPv4-D16 have Parity & ECC, FPU / NEON / Jazelle RCT and MMU + TrustZone DBX / Hardware virtualization, in-order execution, superscalar, 14 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8-10 stage [22] pipeline, low-power design Cortex-A8
[23]

1.9 DMIPS / MHz per core

Application profile, ARM / Thumb 16-32 KB / 16-32 KB up to 2000 (2.0 / Thumb-2 / VFPv3 FPU / L1, 0-1 MB L2 opt DMIPS/MHz in speed Optional NEON / Jazelle RCT and ECC, MMU + from 600MHz to greater DAC, 13-stage superscalar TrustZone than 1GHz) pipeline 2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2GHz on Performance Optimized TSMC 40G (dual core)

Cortex-A9 MPCore Application profile, ARM / Thumb 16-64 KB / 16-64 KB [24] / Thumb-2 / DSP / Optional L1, 0-8 MB L2 opt VFPv3 FPU / Optional NEON / Parity, MMU + Jazelle RCT and DBX, TrustZone out-of-order speculative issue superscalar, 14 SMP cores, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) ARM Cortex-A12
[25]

Application profile, ARM / 32-64KB / 32 KB L1, Thumb-2 / DSP / VFPv4 FPU / 256KB-8 MB L2 NEON / Hardware virtualization, out-of-order speculative issue superscalar, 14 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) Application profile, ARM / Thumb 32 KB / 32 KB L1, At least 3.5 DMIPS/MHz / Thumb-2 / DSP / VFPv4 FPU / 0-4 MB L2, L1 & L2 per core (Up to 4.01 have Parity & ECC, DMIPS/MHz depending NEON / Jazelle RCT / Hardware [27] MMU + TrustZone virtualization, out-of-order on implementation). speculative issue superscalar, 14 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, [22] 15-24 stage pipeline

Cortex-A15 [26] MPCore

List of ARM microprocessor cores

[28]

6
Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, multi-issue, deeply out-of-order pipeline Feature 8~64KB/8~64KB L1 per core, 128KB~2MB L2 shared, 40-bit physical addresses 2.3 DMIPS/MHz

Cortex-A50

ARMv8-A

Cortex-A53

Cortex-A57

[29]

48KB/32KB L1 per At least 4.1 DMIPS/MHz core, 512KB~2MB per core (Up to 4.76 L2 shared, 44-bit DMIPS/MHz depending physical addresses on implementation).

ARM Family

ARM Architecture

ARM Core

Cache (I/D), MMU

Typical MIPS @ MHz

Designed by third parties

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.
Family ARM Architecture ARMv4 Core Feature Cache (I/D), MMU Typical MIPS @ MHz 133206MHz 1.0 DMIPS/MHz 1.26 DMIPS/MHz 100-200 MHz 1.26 MIPS/MHz 166-300 MHz 1.35 DMIPS/MHz 500 MHz 1.22 DMIPS/MHz 200 MHz 1.43 MIPS/MHz 800 MHz 1.43 MIPS/MHz 500 MHz 2.4 DMIPS/MHz 1000 MHz 32 KB/32 KB, MMU 133400MHz

StrongARM
[30]

SA-1

5-stage pipeline

16 KB/816 KB, MMU up to 32 KB / 32 KB Cache, MPU

Faraday

ARMv4

FA510

6-stage pipeline

FA526

up to 32 KB / 32 KB Cache, MMU 8-stage pipeline 32 KB/32 KB Cache, MMU

FA626

ARMv5TE

FA606TE

5-stage pipeline

no cache, no MMU

FA626TE

8-stage pipeline

32 KB/32 KB Cache, MMU

FMP626TE

8-stage pipeline, SMP

FA726TE

13 stage pipeline, dual issue

XScale

ARMv5TE

XScale

7-stage pipeline, Thumb, Enhanced DSP instructions Wireless MMX, Wireless SpeedStep added Wireless MMX2 added

Bulverde Monahans
[]

32 KB/32 KB, MMU 32 KB/32 KB (L1), optional L2 cache up to 512 KB, MMU

312624MHz up to 1.25GHz

List of ARM microprocessor cores

7
Feroceon Jolteon PJ1 (Mohawk) 5-8 stage pipeline, single-issue 5-8 stage pipeline, dual-issue 5-8 stage pipeline, single-issue, Wireless MMX2 16 KB / 16 KB, MMU 32 KB / 32 KB, MMU 32 KB / 32 KB, MMU 1.46 DMIPS/MHz 1.06 GHz 2.41 DMIPS/MHz 1.6 GHz 2.1 DMIPS / MHz per core 600-2000 MHz

Sheeva

ARMv5

ARMv6/ARMv7-A

PJ4

6-9 stage pipeline, dual-issue, Wireless MMX2, SMP

32 KB / 32 KB, MMU

Snapdragon

ARMv7-A

Scorpion
[31]

Used by some members of the Snapdragon S1, S2, and S3 families. 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide) Used by some members of the Snapdragon S4 family. 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide) Custom ARM core used in the Apple A6 and Apple A6X. 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON 64 bit, quad issue, SMP

256 KB L2 per core

Krait

[31]

4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core

3.3 DMIPS / MHz per core

Apple Ax

ARMv7-A

Apple Swift
[]

L1: 32 kB instruction + 32 kB data, L2: 1 MB

3.5 DMIPS / MHz Per Core

X-Gene

ARMv8-A

X-Gene

Cache, MMU, Virtualization

3 GHz

Denver

ARMv8-A

64 bit

References
[4] . [5] Register 13, FCSE PID register (http:/ / infocenter. arm. com/ help/ topic/ com. arm. doc. ddi0151c/ I47491. html) ARM920T Technical Reference Manual [8] Cortex-M0 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-m/ cortex-m0. php?tab=Specifications) [9] Cortex-M0/M0+/M1 Instruction Set; ARM Holding. (http:/ / archive. electronicdesign. com/ files/ 29/ 20719/ fig_01. gif) [10] Cortex-M0+ Specification Summary; ARM Holdings. (http:/ / www. arm. com/ products/ processors/ cortex-m/ cortex-m0plus. php) [11] Cortex-M1 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-m/ cortex-m1. php?tab=Specifications) [12] "ARM Extends Cortex Family with First Processor Optimized for FPGA" (http:/ / www. arm. com/ news/ 17017. html), ARM press release, March 19, 2007. Retrieved April 11, 2007. [13] "ARM Cortex-M1" (http:/ / www. arm. com/ products/ CPUs/ ARM_Cortex-M1. html), ARM product website. Retrieved April 11, 2007. [14] Cortex-M3 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-m/ cortex-m3. php?tab=Specifications) [15] Cortex-M4 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-m/ cortex-m4-processor. php?tab=Specifications) [16] Cortex-R4 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-r/ cortex-r4. php?tab=Specification) [17] Cortex-R5 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-r/ cortex-r5. php) [18] Cortex-R5 & Cortex-R7 Press Release; ARM Holdings; January 31, 2011. (http:/ / arm. com/ products/ arm-expands-unmatched-real-time-cortex-processor-portfolio. php) [19] Cortex-R7 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-r/ cortex-r7. php?tab=Specification) [20] Cortex-A5 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-a/ cortex-a5. php?tab=Specifications) [21] Cortex-A7 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-a/ cortex-a7. php?tab=Specifications) [22] Deep inside ARM's new Intel killer; The Register; October 20, 2011. (http:/ / www. theregister. co. uk/ 2011/ 10/ 20/ details_on_big_little_processing/ ) [23] Cortex-A8 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-a/ cortex-a8. php?tab=Specifications) [24] Cortex-A9 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-a/ cortex-a9. php?tab=Specifications) [25] Cortex-A12 Summary; ARM Holdings. (http:/ / www. arm. com/ products/ processors/ cortex-a/ cortex-a12-processor. php) [26] Cortex-A15 Specification Summary; ARM Holdings. (http:/ / arm. com/ products/ processors/ cortex-a/ cortex-a15. php?tab=Specifications) [27] Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 | ITProPortal.com (http:/ / www. itproportal. com/ 2011/ 03/ 14/ exclusive-arm-cortex-a15-40-cent-faster-cortex-a9/ )

List of ARM microprocessor cores

[30] (http:/ / www. faraday-tech. com/ html/ documentation/ download/ Faraday_CPU_roadmap_FTC-2011-01. pdf) [31] Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored; Anandtech. (http:/ / www. anandtech. com/ show/ 4940/ qualcomm-new-snapdragon-s4-msm8960-krait-architecture)

Further reading
The Definitive Guide to the ARM Cortex-M0; 1st Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN 978-0-12-385477-3. (Online Sample) (http://books.google.com/books?id=5OZblBzjsJ0C& printsec=frontcover&dq=isbn:9780123854773) The Definitive Guide to the ARM Cortex-M3; 2nd Edition; Joseph Yiu; Newnes; 480 pages; 2009; ISBN 978-1-85617-963-8. (Online Sample) (http://books.google.com/books?id=mb5d_xeINZEC& printsec=frontcover&dq=isbn:9781856179638)

Article Sources and Contributors

Article Sources and Contributors

List of ARM microprocessor cores Source: http://en.wikipedia.org/w/index.php?oldid=558126067 Contributors: Arndbergmann, Bender235, C933103, Coolbho3000, DmitryKo, Gabi.davar, Garysims, Gogo Dodo, Imroy, Matthew Anthony Smith, MoreNet, Mtpaley, Sae1994, Sbmeirow, Sfm 7, Sun Creator, Trevj, Vincent Liu, Zxb, 24 anonymous edits

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