HY62256B Series

32Kx8bit CMOS SRAM

DESCRIPTION
The HY62256B is a high-speed, low power and 32,786 X 8-bits CMOS Static Random Access Memory fabricated using Hyundai's high performance CMOS process technology. It is suitable for use in low voltage operation and battery back-up application. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0 volt.

FEATURES
Fully static operation and Tri-state output TTL compatible inputs and outputs Low power consumption Battery backup(L/LL-part) - 2.0V(min.) data retention Standard pin configuration - 28 pin 600 mil PDIP - 28 pin 330mil SOP - 28 pin 8x13.4 mm TSOP-I (Standard and Reversed) Standby Current(uA) L LL 1mA 100 25 Temperature (C) 0~70(Normal)

Product Voltage Speed No. (V) (ns) HY62256B 5.0 55/70/85 Note 1. Current value is max.

Operation Current(mA) 8

PIN CONNECTION
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4

A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

Vcc /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4

/OE A11 A9 A8 A13 /WE Vcc A14 A12 A7 A6 A5 A4 A3

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2

A3 A4 A5 A6 A7 A12 A14 Vcc /WE A13 A8 A9 A11 /OE

14 13 12 11 10 9 8 7 6 5 4 3 2 1

15 16 17 18 19 20 21 22 23 24 25 26 27 28

A2 A1 A0 I/O1 I/O2 I/O3 Vss I/O4 I/O5 I/O6 I/O7 I/O8 /CS A10

PDIP

SOP

TSOP-I(Standard)

TSOP-I(Reversed)

PIN DESCRIPTION
Pin Name /CS /WE /OE A0 ~ A14 I/O1 ~ I/O8 Vcc Vss Pin Function Chip Select Write Enable Output Enable Address Inputs Data Input/Output Power(+5.0V) Ground
A0

BLOCK DIAGRAM
SENSE AMP ROW DECODER ADD INPUT BUFFER I/O1 OUTPUT BUFFER I/O8

COLUMN DECODER

A14 /CS /OE /WE

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.04 /Jan.99 Hyundai Semiconductor

CONTROL LOGIC

WRITE DRIVER

MEMORY ARRAY 512x512

HY62256B Series

ORDERING INFORMATION
Part No. HY62256BP HY62256BLP HY62256BLLP HY62256BJ HY62256BLJ HY62256BLLJ HY62256BT1 HY62256BLT1 HY62256BLLT1 HY62256BR1 HY62256BLR1 HY62256BLLR1 Speed 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 Power L-part LL-part L-part LL-part L-part LL-part L-part LL-part Package PDIP PDIP PDIP SOP SOP SOP TSOP-I Standard TSOP-I Standard TSOP-I Standard TSOP-I Reversed TSOP-I Reversed TSOP-I Reversed

ABSOLUTE MAXIMUM RATING (1)

Symbol Vcc, VIN, VOUT TA TSTG PD IOUT TSOLDER Parameter Power Supply, Input/Output Voltage Operating Temperature Storage Temperature Power Dissipation Data Output Current Lead Soldering Temperature & Time Rating -0.5 to 7.0 0 to 70 -65 to 150 1.0 50 260 10 Unit V C C W mA Csec

Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

Symbol Vcc Vss VIH VIL Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 Max. 5.5 0 Vcc+0.5 0.8 Unit V V V V

Note 1. VIL = -3.0V for pulse width less than 30ns

TRUTH TABLE
/CS H L L L /WE X H H L /OE X H L X Mode Standby Output Disabled Read Write I/O Operation High-Z High-Z Data Out Data In

Note 1. H=VIH, L=VIL, X=Don't Care

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HY62256B Series

DC CHARACTERISTICS
Vcc = 5V 10%, TA = 0C to 70C (Normal), unless otherwise specified. Symbol Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc ILO Output Leakage Current Vss < VOUT < Vcc, /CS = VIH or /OE = VIH or /WE = VIL Icc Operating Power Supply /CS = VIL, Current VIN = VIH or VIL, II/O = 0mA ICC1 Average Operating Current /CS = VIL, Min. Duty Cycle = 100%, II/O = 0mA ISB TTL Standby Current /CS= VIH (TTL Inputs) ISB1 CMOS Standby Current /CS > Vcc - 0.2V (CMOS Inputs) L LL VOL Output Low Voltage IOL = 2.1mA VOH Output High Voltage IOH = -1mA Note : Typical values are at Vcc =5.0V, TA = 25C Min. -1 -1 2.4 Typ. 5 30 0.4 2 1.5 Max. 1 1 8 60 1 1 100 25 0.4 Unit uA uA mA mA mA mA uA uA V V

AC CHARACTERISTICS(I)
Vcc = 5V 10%, TA = 0C to 70C (Normal) unless otherwise specified. -55 # Symbol Parameter Min. Max. READ CYCLE 1 tRC Read Cycle Time 55 2 tAA Address Access Time 55 3 tACS Chip Select Access Time 55 4 tOE Output Enable to Output Valid 25 5 tCLZ Chip Select to Output in Low Z 5 6 tOLZ Output Enable to Output in Low Z 5 7 tCHZ Chip Disable to Output in High Z 0 20 8 tOHZ Out Disable to Output in High Z 0 20 9 tOH Output Hold from Address Change 5 WRITE CYCLE 10 tWC Write Cycle Time 55 11 tCW Chip Selection to End of Write 50 12 tAW Address Valid to End of Write 50 13 tAS Address Set-up Time 0 14 tWP Write Pulse Width 40 15 tWR Write Recovery Time 0 16 tWHZ Write to Output in High Z 0 20 17 tDW Data to Write Time Overlap 25 18 tDH Data Hold from Write Time 0 19 tOW Output Active from End of Write 5 -70 Min. Max. 70 5 5 0 0 5 70 65 65 0 50 0 0 35 0 5 70 70 35 30 30 30 -85 Min Max. 85 5 5 0 0 5 85 75 75 0 60 0 0 40 0 5 85 85 45 30 30 30 -

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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HY62256B Series

AC TEST CONDITIONS
TA = 0C to 70C (Normal) / -40C to 85C (E.T.) unless otherwise specified. Parameter Value Input Pulse Level 0.8V to 2.4V Input Rise and Fall Time 5ns Input and Output Timing Reference Levels 1.5V Output Load CL = 100pF + 1TTL Load

AC TEST LOADS
TTL

CL(1)

Note : Including jig and scope capacitance

CAPACITANCE
TA = 25C, f = 1.0MHz Symbol Parameter CIN Input Capacitance CI/O Input /Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF

Note : These parameters are sampled and not 100% tested

TIMING DIAGRAM
READ CYCLE 1
tRC ADDR tAA OE tOE tOLZ CS tACS tCLZ Data Out High-Z Data Valid tOHZ tCHZ tOH

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HY62256B Series

Note(READ CYCLE): 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and arenot referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for the read cycle.

READ CYCLE 2
tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH

Note(READ CYCLE): 1. /WE is high for the read cycle. 2. Device is continuously selected /CS= VIL. 3. /OE =VIL.

WRITE CYCLE 1(/OE Clocked)

tWC ADDR

OE tAW tCW CS tAS WE tDW Data In tOHZ

Data Out

tWP

tWR

tDH Data Valid

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HY62256B Series

WRITE CYCLE 2 (/OE Low Fixed)

tWC ADDR tAW tCW CS tAS WE tDW Data In tWHZ Data Out tDH Data Valid tOW (7) (8) tWP tWR

Notes(WRITE CYCLE): 1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to the end of write . 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS, or /WE going high. 5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state, input of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of the new address.

DATA RETENTION CHARACTERISTIC

TA=0C to 70C (Normal) Symbol Parameter VDR Vcc for Data Retention ICCDR Data Retention Current Test Condition CS>Vcc-0.2V, Vss<VIN<Vcc Vcc=3.0V, L /CS>Vcc - 0.2V, LL Vss<VIN<Vcc See Data Retention Timing Diagram Min 2.0 0 tRC(2) Typ 1 1 Max 50 15 Unit V uA uA ns ns

tCDR tR

Chip Deselect to Data Retention Time Operating Recovery Time

Notes 1. Typical values are under the condition of TA = 25C. 2. tRC is read cycle time.

Rev.04 /Jan.99

HY62256B Series

DATA RETENTION TIMING DIAGRAM

VCC 4.5V tCDR DATA RETENTION MODE tR

2.2V VDR CS>VCC-0.2V CS VSS

RELIABILITY SPEC.
TEST MODE ESD HBM MM LATCH - UP TEST SPEC. > 2000V > 250V < -100mA > 100mA

PACKAGE INFORMATION
28pin 600mil Dual In-Line Package(P)

UNIT : INCH(mm)

MAX. MIN.

1.467(37.262) 1.447(36.754) 0.600(15.240)BSC 0.090(2.286) 0.070(1.778) 0.065(1.650) 0.050(1.270) 0.155(3.937) 0.145(3.683) 0.035(0.889) 0.020(0.508) 0.550(13.970) 0.530(13.462)

0.140(3.556) 0.021(0.533) 0.100(2.54)BSC 0.015(0.381) 0.120(3.048)

3 deg 11 deg

0.014(0.356) 0.008(0.200)

Rev.04 /Jan.99

HY62256B Series

28pin 330mil Small Outline Package(J)

0.346(8.788) 0.338(8.585) 0.480(12.192) 0.460(11.684)

UNIT : INCH(mm)

MAX . MIN.

0.728(18.491) 0.720(18.288)

0.110(2.794) 0.094(2.388) 0.014(0.356) 0.002(0.051) 0.012(0.305) 0.008(0.203) 0.050(1.270) 0.030(0.762)

0.050(1.270)BSC

0.020(0.508) 0.014(0.356)

28pin 8x13.4mm Thin Small Outline Package Standard(T1)

UNIT : INCH(mm)

MAX. MIN.

0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2)

0.319(8.1) 0.311(7.9)

0.040(1.02) 0.036(0.91) 0.008(0.20) 0.002(0.05)

0.027(0.7) 0.012(0.3)

0.008(0.2) 0.004(0.1)

0.022(0.55 BSC)

Rev.04 /Jan.99

HY62256B Series

28pin 8x13.4mm Thin Small Outline Package Reversed(R1)

UNIT : INCH(mm)

MAX. MIN.

0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2)

0.319(8.1) 0.311(7.9)

0.040(1.02) 0.036(0.91) 0.008(0.20) 0.002(0.05)

0.027(0.7) 0.012(0.3)

0.008(0.2) 0.004(0.1)

0.022(0.55 BSC)

Rev.04 /Jan.99