IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO.

1, JANUARY 2002

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A Power-Efficient Wide-Range Phase-Locked Loop

Oscal T.-C. Chen, Member, IEEE, and Robin Ruey-Bin Sheen
AbstractThis work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider. The phase/frequency detector and charge pump are designed to reduce the dead zone and charge sharing for enhancing the locking performance, respectively. In the design of the range-programmable voltage-controlled oscillator, the original inverter ring of a delay line is divided into several smaller ones, and then they are recombined in parallel to each other. Programming the number of paralleled inverter rings allows us to generate the wide-range clock frequencies. This design shuts off some inverters that are not in use to reduce power consumption. To allow the phase-locked loop to shut off inverters, the feasibility of using controllable inverters by the output-switch and power-switch schemes is explored. Theoretical analyses indicate that power consumption of the voltage-controlled oscillator depends on transistors sizes rather than operating frequencies. By applying the TSMC 0.35- m CMOS technology, the proposed phase-locked loop that uses the power-switch scheme can yield clock signals ranging from 103 MHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, power dissipation that is proportional to the number of paralleled inverter rings is measured with 1.32 to 4.59 mW. The phase-locked loop proposed herein can be used in various digital systems, providing power-efficient and wide-range clock signals for task-oriented computations. Index TermsClock generator, low power, phase-locked loop, voltage-controlled oscillator.

I. INTRODUCTION DVANCES in microelectronic technologies have led to the integration of millions or billions of transistors in a single chip capable of operating at a high clock frequency to provide large computation capabilities [1]. When utilized to enhance multimedia computing and communications, this microelectronic chip or processor must manipulate various media such as image, video, speech, audio, graphics, and text. The computational complexities markedly differ for various media applications and network transmission rates. The availability of a processor capable of operating at distinct clock frequencies to fulfill the real-time requirements of various media applications would make it feasible to efficiently use power to accomplish desired tasks. In addition, when portable devices and mobile phones operating at idle, stand-by, and active modes are considered, the clock generator must provide different output frequencies in a low-power operation manner. To implement an on-chip clock generator, the charge-pump phased-locked loop (PLL), which is easily realized by integrated
Manuscript received November 7, 2000; revised June 21, 2001. This work was supported in part by the National Science Council, Taiwan, under Contract NSC 88-2736-L-194-003. The authors are with Signal and Media Laboratories, Department of Electrical Engineering, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C. (e-mail: [email protected]). Publisher Item Identifier S 0018-9200(02)00133-6.

circuits as having low power dissipation, is widely adopted [2], [3]. The modified phase detector and charge pump have been extensively used to enhance the performance of the PLL [4][7]. To reduce phase noises, Young proposed a tri-state phase/frequency detector that can detect lead or lag of the phases and frequencies of two signals, thus lessening the locking time [4]. Kaenel et al. developed a circuit to reduce the dead zone of a phase/frequency detector [5]. The charge sharing during transistors switching of the charge pump can lead to a large jitter of the PLL. Some studies have modified the charge-pump circuits to minimize the jitter [6], [7]. The voltage-controlled oscillator (VCO) is an integral part of the PLL for producing clock signals. In the on-chip PLL design, the inverter ring with a controllable delay is popularly used [8][10]. Due to a low supply voltage, the frequency range controlled by the output from the loop filter is also decreased, thereby limiting the output range of the VCO. Hence, some researchers enlarged or programmed the driving capabilities, loading capacitors, or number of inverter stages for changing the delays to generate output signals of the VCO with wide-range frequencies [11][14]. An efficient design in the generation and synthesis of clock signals is essential to generate different clock frequencies. The PLL with a programmable divider, shown in Fig. 1(a), is most widely adopted to generate clock signals [2], [5]. Selecting the division factor of a programmable divider allows the PLL to generate the required output frequency. When the supply voltage becomes lower, the frequency range of the VCO is also reduced. To provide a sufficient output frequency range, designing the PLL with a wider range is more difficult. In addition, a wide range of the output frequencies versus a small range of the controlled voltage could produce a loop with a wide bandwidth that is sensitive to noise disturbances. This effect can make the loop system unstable, thereby increasing the design cost. Another approach uses a phase-locked loop and a frequency-synthesizing unit, as shown in Fig. 1(b) [15]. The phase-locked loop generates the highest clock frequency that is then synthesized by the frequency-synthesizing unit to generate different clock signals. This approach can yield any clock frequency from the maximum frequency of the PLL to zero. However, when a low clock frequency is required, power consumption is wasted, as the VCO needs a large amount of current to generate the maximum clock frequency. This work develops an approach that incorporates the range-programmable voltage-controlled oscillator in a phase-locked loop to generate wide-range clock frequencies in a low-power dissipation manner, as shown in Fig. 2. Various wide-range output frequencies of the PLL can be achieved by using the range-programmable VCO and programmable divider. The range-programmable VCO is composed of many paralleled inverter rings. The output frequency range is deter-

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Fig. 2. Proposed wide-range clock generator.

Fig. 1. Conventional clock generators. (a) PLL with programmable divider. (b) PLL with frequency synthesizer.

mined by programming the number of paralleled inverter rings. To allow the phase-locked loop to shut off inverters, this study also examines the feasibility of adopting two types of controllable inverters that use the output-switch and power-switch schemes. Our theoretical analyses demonstrate that power consumption of the VCO depends on the size of the VCO transistors rather than the operating frequency. In addition to the range-programmable VCO, the phase/frequency detector and charge pump are improved as well. By using the TSMC 0.35- m CMOS technology, the proposed phase-locked loop using the power-switch scheme at a supply voltage of 1.8 V can generate output signals ranging from 103 MHz to 1.02 GHz. Depending on and proportional to the number of paralleled inverter rings of the range-programmable VCO, the power consumption of the proposed PLL ranges from 1.32 to 4.59 mW. Therefore, it can generate wide-range clock frequencies for various industrial applications in a power-efficient manner.

require any inductor. This ring oscillator can be implemented by an odd number of inverters with voltage-controlled delay elements each of which includes a voltage-controlled nMOS transistor and a capacitor as shown in Fig. 3. This nMOS transistor acts as a voltage-controlled resistor that can adjust the RC time constant between two inverter stages. Hence, controlling the delays among inverter stages allows us to generate the required oscillation frequency. To understand the VCO, this study analyzes the operational principle of an inverter. Generally, the CMOS inverter includes two transistors of the pMOS and nMOS types. In addition to that the static power dissipation of an inverter is close to zero, its symmetric architecture is easily implemented and widely used. When switching between on and off, the MOS transistor transfers the operations among saturation, triode, and cutoff regions. Based on the current equation of the MOS transistor, the period of an inverter changing from logic-1 to logic-0 is can be analyzed in two parts. First, the output voltage to , where the nMOS transistor changed from is the threshold voltage. The is at a saturation mode and and time can be described as relationship between (1) is the loading capacitor, and the gain factor is equal where . In addition, is the electron mobility and to is the oxide capacitance. and are the width and length can be easily of a transistor, respectively. Hence, this period derived as

(2) The second part is the period of the transistor operating at the triode region. The relationship between the output voltage and time can be illustrated as (3)

II. ANALYSES OF POWER CONSUMPTION AND FREQUENCY RANGES OF VCOS In the CMOS technology, a ring oscillator structure is frequently used as the basis for the VCO design because it does not

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Fig. 3.

Voltage-controlled oscillator.

According to (3), when the output voltage is changed from to , the period can be derived as

Fig. 4. Three inverters in a ring structure and their operations. (a) Three-inverter ring. (b) Simulated operations.

(4) According to the above equation, the output voltage derived as can be where and are the transient currents of nMOS and pMOS and , respectively. with values of In the charging and discharging modes, the output voltages are to , and from to , respectively, where changed from is the maximum value of the output voltage, and is the minimum. Equation (7) can be modified to

(5)

The falling time of the inverters output from and to become

to

sums

(8) The short-circuit power dissipation occurs at the transient period of nMOS and pMOS transistors being active simultaneously. This power consumption, although not related to the loading capacitor, is related to transistors sizes. It can be interpreted by [16] (9) Fig. 4 shows three inverters in a ring structure and their simulated operations. When the output signal of the first inverter to 0.5 , the second inverter starts to is changed from be activated for charging. According to (2) and (4), this period equals plus where is the time of the inverters to 0.5 . When the second output changing from , the third inverter inverters output is charged from 0 to 0.5 begins to be discharged. This period is denoted by . The rising and falling time of these inverters are adjusted to be the same is equal to . In the same manner, the output of such that , and the first the third inverter becomes smaller than 0.5

(6) In the same manner, the rising time of the inverters output is sefrom logic-0 to logic-1 can be formulated. Usually, equal to . lected to be the same as , thereby making or in the following equaHerein, is used to represent tions. Major power dissipation in the CMOS circuits can be classified as dynamic and short-circuit ones. The dynamic power dissipation originates from the charging and discharging of the loading capacitor. If the period of signals is , the dynamic power consumption of an inverter can be represented by

(7)

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For example, when is equal to 3, is 1.8 V, and is is around 0.066 V. In the same manner, 0.62 V, the value of the maximum voltage of the symmetric inverters output can . Equation (11) reveals that, be derived to be around although unaffected by the transistors sizes and loading capacitors, the minimum and maximum values of output signals are related to the supply voltage, threshold voltage, and number of and 0, respecinverter stages. When and are close to tively, the power consumption of an inverter in the ring oscillator can be derived according to (8) and (10).

Fig. 5. Relationship between

N and K .

inverters output is changed from discharging to charging operation modes. Therefore, we can obtain a half period of the VCO equal to summation of the first inverters , the second can be derived inverters , and the third inverters . The as

(10)

(12)

In a three-inverter ring structure, the complete falling time such that the peof each inverter can be represented by . The operational frequency of riod of the VCO becomes . By changing the values of and of the VCO is (10), the VCO can generate different output frequencies. In addition to using three inverters in a ring structure, the other odd numbers of inverter stages can be utilized to obtain different output frequencies. When the number of inverter stages is , , the a half period of the VCO includes the first inverters , the third inverters and the th second inverters inverters . Hence, the output frequency of the VCO can be . When the first inverters output is discharged from to , this period is the summation of the first inverters delay , the second inverters delay , the third inverters delay and the th inverters . According to (2), (5), and of the first inverters output can (10), the minimum voltage be derived as

The dynamic power consumption of an inverter is proportional to the gain factor but inversely proportional to the number of inverter stages. During analysis of the short-circuit power dissipation, the rising and falling time of an inverter stage is represented by the to 0.9 and periods of its output changing from 0.1 to 0.1 , respectively. According to (11), when from 0.9 becomes 0.1 , the required number of inverter stages, to interpret the falling time of which can be multiplied with , can be derived as

(13)

(11)

. Fig. 5 shows the relationship bewhere is equal to and . In most CMOS circuits, can range from tween 0.1 to 0.5 and then the value of ranges between 2.1 and 2.6. Since the number of inverter stages of the VCO is larger than or equal to 3, the falling and rising time would become the constant values. In other words, once the supply voltage and manufacture process are determined, the factor that is multiplied with and to interpret the falling and rising time is a fixed value,

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TABLE I CHARACTERISTIC COMPARISON OF THE PROPOSED AND CONVENTIONAL APPROACHES TO DESIGN THE WIDE-RANGE VCOS

respectively. When the rising time is equal to the falling time, (9) can be modified to

(13) Hence, the short-circuit power consumption of an inverter is also proportional to the gain factor and inversely proportional to the number of inverter stages. The total power consumption of the VCO can be expressed as

(14) Power consumption of a ring oscillator depends on , and is . Once the transistors sizes of inverter independent of and stages are selected, power dissipation of the ring oscillator is determined. In other words, the operational frequency does not affect power consumption of the ring oscillator.

The proposed range-programmable VCO includes many controllable inverter rings in parallel. For a high oscillation frequency, all inverter rings are used to increase the value of , whereas for a low oscillation frequency, some inverter rings are shut off to decrease the value of . Hence, the power consumption of the proposed VCO to generate a low oscillation frequency can be minimized according to (14). Table I compares the characteristics of the proposed and conventional approaches to design the wide-range VCOs. The total delay of all inverter stages, which determines the output frequency of the VCO, is related to the driving capabilities, equivalent loading capacitors and number of inverter stages. Therefore, designing a wide-range output frequency either involves changing or programming the driving capabilities, equivalent loading capacitors, and number of inverter stages. Table I reveals that although directly enlarging the driving capability and loading capacitor of each stage could increase the output frequency range of the VCO, the gain of the VCO becomes larger. This effect makes the VCO sensitive to noise, thereby worsening the jitter performance. Hence, these two approaches are inadequate in a lowvoltage operation system. To operate at a low supply voltage, the wide frequency range can be partitioned into many small portions that are individually addressed by the control voltages. In such an approach, the gain of the VCO can be adequately minimized to stabilize the system. Hence, programming the driving capabilities, equivalent loading capacitors, and the number of inverter stages are the preferred approaches. In programming the number of inverter stages, the larger the number of inverter stages utilized implies a smaller output frequency. More hardware components are necessary to realize more inverter stages for programmable operations. The approach of programming the loading capacitors among inverter stages may require a lot of areas to implement these capacitors. In addition, the power consumption cannot be minimized when using a small capacitor. The proposed approach uses many paralleled inverter rings that can be viewed as programming driving capabilities of inverter stages. In addition, a fairly low hardware complexity is needed. In particular, the power consumption can be reduced due to the VCO operating at a low oscillation frequency. Therefore, the proposed range-programmable VCO can be applied in a low supply voltage with a power-efficient operation.

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Fig. 6.

Proposed phase/frequency detector.

III. PROPOSED PHASE-LOCKED LOOP The proposed phase-locked loop consists of a phase/frequency detector, charge pump, second-order passive loop filter, range-programmable voltage-controlled oscillator, and programmable divider, as shown in Fig. 2. The phase/frequency detector identifies the phase and frequency differences between the external reference signal and the internal signal from the programmable divider. When the charge pump and loop filter are used, these differences are converted into a control voltage to adjust the output frequency of the voltage-controlled oscillator. Until the frequency and phase of the external reference signal are the same as those of the internal signal from the programmable divider, a fixed value of the output signal from the loop filter is not generated to control the VCO for yielding a constant output frequency. The detailed functional units of the proposed PLL are described as follows. A. Phase/Frequency Detector In addition to the phase difference, the proposed phase/frequency detector compares the external reference signal and the signal from the programmable divider to determine their frequency difference; doing so would reduce the lock-in time. Owing to the size of the dead zone determining the phase noise of the PLL, this study also proposes a modified tri-state phase/frequency detector with the asynchronous race-free characteristic as shown in Fig. 6. In this design, signal edges are detected by the flip-flops capable of providing a high-accuracy detection and performing at a high-frequency operation. The state switching of the proposed phase/frequency detector uses a NOR gate to reset the flip flops in order to minimize the dead zone. In addition, a XNOR and two AND gates are applied to eliminate two output signals and being logic-1 simultaneously. Hence, the short-circuit effect in the charge pump can be avoided. Fig. 7 shows the operations of the proposed and conventional phase/frequency detectors [5]. Two and are shown in Fig. 7(a) input signals of is leading . In the operations of the where conventional phase/frequency detector as shown in Fig. 7(b), the signals of and may yield the periodical step and pulse functions, respectively. Of which overlapping periods lead to a short circuit in the charge pump. In the operations of the proposed phase/frequency detector as shown in Fig. 7(c), there is no the pulse in the signal , thus preventing a short circuit

Fig. 7. Operations of the proposed and conventional phase/frequency detector. (a) Two input signals. (b) Simulated output signals of conventional phase/frequency detector. (c) Simulated output signals of the proposed phase/frequency detector. (d) Simulated output voltages of the charge pump using the proposal and conventional phase/frequency detector.

in the charge pump. Fig. 7(d) shows the simulated output voltages of the charge pump using the proposed and conventional phase/frequency detectors. This figure indicates some ripples in the output signal of the charge pump when using the conventional phase/frequency detector. By using the proposed phase/frequency detector to eliminate the short-circuit effect,

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Fig. 8. Proposed charge pump.

the charge pump yields the output signal without any ripple, thereby stabilizing the PLL system relatively easily. B. Charge Pump In the proposed charge pump shown in Fig. 8, the transistors of M1 and M2 are used to discharge and charge the nodes of and when transistors M3 and M4 are inactive, respectively. In such a design, the charge sharing is minimized. The transistors of M3 and M4 addressed by signals of and act as switches, respectively. Despite the on/off controls of these two transistors, the charge pump can charge or discharge the capacitor of the loop filter to convert the phase and frequency differences into a relevant control voltage. The transistors of M5 and M7 and of M6 and M8 individually form the current mirrors to pull the output node up and down quickly, respectively. To minimize the power consumption, these two current sources are controlled by transistors of M9 and M10 which are addressed by signals of and , respectively. Compared to the conventional charge pump that has the switch in source [7], the proposed charge pump can have the full-swing output of that is applicable in a lowand voltage operation. By setting the and nodes to , respectively, the transistors of M3 and M4 can be operated at the saturation region to eliminate a large instantaneous current can be during the transition. Hence, the output voltage of generated more stably. C. Loop Filter The loop filter performs like a filter function in terms of eliminating undesired high-frequency noise signals and providing a stable control voltage to the VCO. Herein, adequately selecting the characteristic parameters of two capacitors and a resistor of the passive second-order loop filter allows us to optimize the performance of the phase-locked loop and maintain its stability efficiently [17]. D. Voltage-Controlled Oscillator The VCO is the most important functional unit in a PLL. Its output frequency determines the effectiveness of the PLL. In addition to operating at the highest frequency, this unit consumes the most power in the system. Obviously, this unit is of
Fig. 9. Proposed VCO using paralleled inverter rings.

particular focus to reduce power consumption for the proposed PLL. Equation (14) clearly reveals that power dissipation of the VCO becomes constant and does not vary with the output frequencies once the transistors sizes of the inverter stages are that determined. The output frequency of the VCO is depends on the transistor sizes and loading capacitances of inverter stages according to (10). Hence, the transistor sizes and loading capacitances of original inverter stages are determined to have capability of generating the required highest oscillation frequency. From Fig. 9, this framework breaks down the original inverter that can yield the highest oscillation frequency into several smaller ones and recombines them in parallel to each other. When all the rings of these small inverters are parallel, power dissipation is the same as that of the original ring oscillator structure in generating the highest oscillation frequency. When not requiring a high oscillation frequency, the system can shut off some of the small inverter rings to reduce the output frequency generated by the VCO. In such an approach, each inverter must be designed to be decide on the number controllable. The control signals of paralleled inverter rings needed in the voltage-controlled oscillator, which subsequently generates only the required clock frequency as demanded by the system. In addition to not requiring an additional synthesizing unit to generate wide-range clock frequencies, this design would also shut off some unused inverters to reduce power consumption. To allow the system to shut off inverters, two types of controllable inverters are designed as shown in Fig. 10. The first is an inverter design using the output-switch scheme, as shown in Fig. 10(a). Herein, we and to a conadd two control transistors addressed by is logic-0 and is logic-1, the ventional inverter. When inverter is enabled to perform its operation. Conversely, when is logic-1 and is logic-0, the inverter is disabled and its output node is floating. However these inverter rings gen-

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TABLE II MEASURED OUTPUT FREQUENCIES

AND POWER CONSUMPTION OF THE CONVENTIONAL VCO, AND THE THE OUTPUT-SWITCH AND POWER-SWITCH SCHEMES

PROPOSED VCOS USING

low clock frequencies. In particular, the range-programmable VCO can overcome small frequency ranges of the PLL at a low supply voltage as well as decrease the ratio of the frequency range versus control voltage swing to enhance noise immunity of the PLL. E. Programmable Divider To reduce power dissipation, the programmable divider is realized by an asynchronous ripple counter using a flip-flop chain, multiplexors, and demultiplexors. Adequately selecting the division factor allows us to generate the required output frequency in the range of the predetermined frequency band of the range-programmable VCO.
Fig. 10. Proposed controllable inverters. (a) An inverter using the output-switch scheme. (b) An inverter using the power-switch scheme.

IV. MEASUREMENT RESULTS The characteristics of the VCO are analyzed herein by designing a conventional VCO and two proposed VCOs using four output-switch and power-switch inverter rings, individand , the total ually. Excluding control transistors of active transistors sizes of four output-switch or power-switch inverters are the same as that of each inverter used in the conventional VCO. In addition, the proposed and conventional VCOs have the same voltage-controlled nMOS transistors and capacitors that are implemented by small transistor sizes and capacitances, respectively, for a low hardware cost and thereby yield a small tuning range of the RC time constant. Table II lists the measured output frequencies and power consumption of these three VCO architectures where denotes the number of paralleled inverter rings. According to this table, the proposed range-programmable VCO architectures can expand the output frequency ranges at a supply voltage of 1.8 V. In line with

erate the highest output frequency, which is smaller than that of the original inverter ring because their charging and discharging currents pass through more transistors, subsequently enlarging the RC time constant between inverters. In light of this consideration, we design another type of a controllable inverter that uses the power-switch scheme, as shown in Fig. 10(b). The two conand trol transistors are individually neighboring to nodes to reduce their impacts on the inverter during charging and discharging operations. This design allows the highest oscillation frequency of the proposed inverter rings to closely resemble that of the original inverter ring. Programming the number of paralleled inverter rings not only significantly increases the output frequency range of the VCO, but also enables the PLL to adjust the output frequency under different demands. Doing so lowers the power consumption not only for the system, but also for the functional unit generating

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Fig. 11. Output frequencies and power dissipation of three VCOs under different control voltages or numbers of paralleled inverter rings. (a) Conventional VCO. (b) Range-programmable VCO using the output-switch scheme. (c) Range-programmable VCO using the power-switch scheme.

the theoretical derivation, power consumption of the VCO is closely related to the transistors sizes, and is independent of the output frequency. The output frequencies of the conventional VCO range from 816 MHz to 1.07 GHz with a power dissipation of 3.92 mW. Closely examining the two proposed range-programmable VCOs reveals that the VCO using the output-switch scheme can generate output frequencies ranging from 84 to 799 MHz. Moreover, its power dissipation is proportional to the number of the paralleled inverter rings, from 1.09 to 4.77 mW. On the other hand, the inverter rings of the VCO designed by the power-switch scheme can generate output frequencies ranging from 103 MHz to 1.02 GHz, and has a power dissipation that is also proportional to the number of paralleled

inverter rings, ranging from 1.07 to 4.19 mW. Therefore, the proposed PLL based on the parallel-structured inverter rings of the VCO using the power-switch scheme can effectively achieve the wide-range and low-power performances. Fig. 11 shows the output frequencies and power dissipation of three VCOs under different control voltages, or number of paralleled inverter rings. The proposed range-programmable VCO can effectively extend the output frequency range. The control transistors are connected to the output node of the inverter during analysis of the VCO using the output-switch scheme. The charging and discharging of the output-switch inverter require passing through the control transistors to yield longer delays. Hence, the maximum frequency of the VCO using the

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TABLE III SPECIFICATIONS OF THE PROPOSED PLL USING THE POWER-SWITCH SCHEME

Fig. 12.

Die photo of the proposed PLL using the power-switch scheme.

the proposed PLL. Table IV compares the proposed and conventional approaches with the wide-range output frequencies [11], are the normalized fre[13], [14]. The factors of , , and quency, gain, and power consumption, respectively, when considering the 0.35- m CMOS technology, a supply voltage of 1.8 V, and an oscillation frequency of 1.02 GHz. These normalized factors are derived by

Technology Technology

(15)

(16) Hz

Fig. 13.

Jitter performance at an input reference frequency of 33 MHz.

Technology

(17)

output-switch scheme is lower than that of the conventional VCO. In the power-switch scheme, the control transistors are moved to the power supply and ground. The control transistors and can be are preset to turn on or off so that the likely connected to the transistors for the inverter operation. This scheme increases the maximum output frequency as well as a wide frequency range. Fig. 11 reveals that the VCO, under different numbers of paralleled inverter rings, can have overlapping output frequency ranges. Closely examining its relationship with power dissipation under different numbers allows us to select a more power-efficient combination to generate output frequency when it falls on the overlapping range. The proposed PLL using the power-switch scheme is implemented by the TSMC 0.35- m 1P4M CMOS technology where the number of paralleled inverter rings of the range-programmable VCO is four. At a supply voltage of 1.8 V, the output frequencies of the PLL range from 103 MHz to 1.02 GHz. Its power consumption is around 1.32 to 4.59 mW. The die photo of the proposed PLL with a size of 0.4 mm 0.4 mm is shown in Fig. 12. Fig. 13 shows a jitter performance at an input reference frequency of 33 MHz. The peak-to-peak jitter is 110 ps and the average jitter is 30 ps. Table III lists the specifications of

where the threshold voltage of an nMOS transistor made by the TSMC 0.35- m CMOS technology is around 0.62 V. Compared to the conventional approaches, the proposed PLL using the range-programmable VCO can have the largest frequency range, a fairly small gain, and power-efficient operation. Particularly in generating a low output frequency, the proposed PLL can effectively scale down its power consumption. Therefore, the PLL proposed herein can be widely utilized in various digital systems for power-efficient operations. V. CONCLUSION This work has developed a wide-range phase-locked loop using the range-programmable voltage-controlled oscillator. The modified phase/frequency detector and charge pump are designed to minimize the dead zone and charging sharing, respectively. The controllable inverter rings of the range-programmable VCO using the output-switch and power-switch schemes are also explored. Experimental results indicate that the power-switch scheme yields a larger frequency range. The relationship that power consumption of the VCO depends on transistor sizes rather than operating frequencies is theoretically formulated and illustrated. By using the TSMC 0.35- m CMOS technology, the designed PLL using the power-switch

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TABLE IV COMPARISON OF THE PROPOSED AND CONVENTIONAL APPROACHES WITH THE WIDE-RANGE OUTPUT FREQUENCIES

scheme can generate clock frequencies ranging from 103 MHz to 1.02 GHz with a power dissipation ranging from 1.32 to 4.59 mW, at a supply voltage of 1.8 V. Upon each systems computing requirement, the number of paralleled inverter rings of the range-programmable VCO can be adjusted to supply different clock frequencies. When a low clock frequency is generated, power consumption of our PLL can be reduced due to shutting off unused inverter rings. Therefore, the proposed wide-range and power-efficient PLL is highly promising for applications in multiple clock operations of digital systems for various task operations.

REFERENCES
[1] W.-K. Chen, The VLSI Handbook. New York: IEEE Press, 2000. [2] B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits. New York: IEEE Press, 1996. [3] A. Chandrakasan and R. Brodersen, Low-Power CMOS Design. New York: IEEE Press, 1998. [4] I. Young, J. Greason, and K. Wong, A PLL clock generator with 5 to 110 MHz of lock range for microprocessors, IEEE J. Solid-State Circuits, vol. 27, pp. 15991607, Nov. 1992. [5] V. Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, A 320MHz, 1.5 mW @ 1.35V CMOS PLL for microprocessor clock generation, IEEE J. Solid-State Circuits, vol. 31, pp. 17151722, Nov. 1996. [6] W. Rhee, Design of low-jitter 1-GHz phase-locked loops for digital clock generation, in Proc. IEEE Int. Symp. Circuits and Systems, 1999, pp. 520523.

[7] P. Larsson, A 21600MHz CMOS clock recovery PLL with low-V capability, IEEE J. Solid-State Circuits, vol. 34, pp. 19511960, Dec. 1999. [8] Y. Savaria, D. Chtchvyrkov, and J. Currie, A fast CMOS voltage-controlled ring oscillator, in Proc. IEEE Int. Symp. Circuits and Systems, 1994, pp. 359362. [9] A. Matsuzawa, Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment, IEEE J. Solid-State Circuits, vol. 29, pp. 470480, Apr. 1994. [10] R.-B. Sheen and O. T.-C. Chen, A 3.3V 600MHz1.30GHz CMOS phase-locked loop for clock synchronization of optical chip-to-chip interconnects, in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, June 1998, pp. 429432. [11] H.-J. Sung, K.-S. Yoon, and H.-K. Min, A 3.3 V high speed CMOS PLL with 3250 MHz input locking range, in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, June 1999, pp. 553556. [12] R.-B. Sheen and O. T.-C. Chen, A wide-range phase-locked loop using a range-programmable voltage-controlled oscillator, in Proc. IEEE 43th Midwest Symp. Circuits and Systems, vol. 1, Aug. 2000, pp. 526529. [13] W. Rhee, A low power, wide linear-range CMOS voltage-controlled oscillator, in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, June 1998, pp. 8588. [14] H. Sutoh, K. Yamakoshi, and M. Ino, A 0.25m CMOS/SIMOX PLL clock generator embedded in a gate array LSI with 5 to 400 MHz lock range, in Proc. IEEE Custom Integrated Circuits Conf., 1997, pp. 4144. [15] J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, A wide-bandwidth low-voltage PLL for PowerPC microprocessors, IEEE J. SolidState Circuits, vol. 30, pp. 383391, Apr. 1995. [16] N. Weste and K. Eshraghian, Principle of CMOS VLSI Design: A Systems Perspective. Boston, MA: Addison-Wesley, 1993. [17] D. Rosemarine, Accurately calculate PLL charge pump filter parameters, Microwaves & RF, pp. 8994, Feb. 1999.

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Oscal T.-C. Chen (M01) was born in Taiwan, R.O.C., in 1965. He received the B.S. degree in electrical engineering from National Taiwan University in 1987, and the M.S. and Ph.D. degrees in electrical engineering from the University of Southern California, Los Angeles, in 1990 and 1994, respectively. He was with the Computer Processor Architecture Department of Computer Communication and Research Labs. (CCL), Industrial Technology Research Institute (ITRI), as a System Design Engineer, Project Leader, and Section Chief from 1994 to 1995. He contributed significantly to many industrial applications including the fuzzy chip, neural networks, speech recognition system, and digital signal processor. He has been an Associate Professor in the Department of Electrical Engineering, National Chung Cheng University (NCCU), Taiwan, since September 1995. Currently, he is also a Director, Industrial Cooperation, The Office of Development and International Cooperation, NCCU. He has served as a Technical Consultant in the Institute for Information Industry, Center for Aviation and Space Technology, and CCL, ITRI. He was a Co-Chair of Southern Telecommunication Center, NSC, Taiwan, from June 1996 to July 1999. His research interests include analog/digital circuit design, video/audio processing, DSP processors, VLSI systems, RF IC, microsensors and communication systems. Dr. Chen was the co-recipient of the Best Paper Award of the IEEE TRANSACTIONS ON VLSI SYSTEMS in 1995. He was an Executive Secretary of VLSI/CAD program, National Science Council (NSC), Taiwan, from 1994 to 1996. He was an Associate Editor of IEEE Circuits and Devices Magazine from July 1995 to March 1999, and a founding member of the multimedia systems and applications technical committee of IEEE Circuits and Systems Society. He participates in the Technical Program Committee of the IEEE International Conference on Multimedia and Expo 20002001. He was the Technical Program Committee and Session Chair of the IEEE Asia Pacific Conference on Circuits and Systems in 1998, the IEEE International Conference on Neural Networks in 1996, and the IEEE International Conference on Computer Design in the Architectures and Algorithm Track in 1994 and 1995. He is a Life Member of the Chinese Fuzzy Systems Association.

Robin Ruey-Bin Sheen received the B.S. and M.S. degrees in electrical engineering from National Chung Cheng University (CCU), Taiwan, R.O.C., in 1996 and 1998, respectively. He is currently working toward the Ph.D. degree in electrical engineering at CCU. His research interests include the design of CMOS mixed-signal integrated circuits for low-power and high-speed data computation and broadband communications.