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Nmos Inverter

1) The document discusses the basic design and operation of an inverter circuit using n-MOS transistors. It describes how a depletion-mode transistor can be used as a pull-up device while an enhancement-mode transistor acts as the pull-down device. 2) It examines how the transfer characteristics and threshold voltage of the inverter can be altered by changing the ratio of the pull-up to pull-down impedances. 3) When cascading multiple inverter stages, it is important to preserve sufficient logic voltage levels. The document provides an analysis to determine an optimal 4:1 pull-up to pull-down ratio for an nMOS inverter driven by another inverter

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lokeshwarrvrjc
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1K views

Nmos Inverter

1) The document discusses the basic design and operation of an inverter circuit using n-MOS transistors. It describes how a depletion-mode transistor can be used as a pull-up device while an enhancement-mode transistor acts as the pull-down device. 2) It examines how the transfer characteristics and threshold voltage of the inverter can be altered by changing the ratio of the pull-up to pull-down impedances. 3) When cascading multiple inverter stages, it is important to preserve sufficient logic voltage levels. The document provides an analysis to determine an optimal 4:1 pull-up to pull-down ratio for an nMOS inverter driven by another inverter

Uploaded by

lokeshwarrvrjc
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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B.

LOKESHWAR RVR & JC College of Engineering

Inverter : basic requirement for producing a complete range of Logic circuits 1 0 0 1

R Vo

R Vss

Vdd
Basic Inverter: Transistor with source connected to ground and a load resistor connected from the drain to the positive Supply rail Output is taken from the drain and control input connected between gate and ground Resistors are not easily formed in silicon - they occupy too much area Transistors can be used as the pull-up device

Pull-Up Vo

Vin

Pull Down Vss

NMOS Depletion Mode Transistor Pull - Up


Pull-Up is always on Vgs = 0; depletion Pull-Down turns on when Vin > Vt Vdd D

With no current drawn from outputs, Ids for both transistors is equal
V0 Vt Vdd Vin

Vo

S D

Non-zero output Vi

Vss

Ids Ids
Vgs=0.2V
DD

Vgs=0
Vgs=-0.2 VDD Vgs=-0.4 VDD Vgs=0.6VDD Vin VDD

Vds Ids

VDD Vds

Vgs=VDD Vgs=0.8VDD Vgs=0.6 VDD

Vgs=0.4 VDD Vgs=0.2VDD


VDD

Vds
VDD

Vo

Vin VDD

Decreasing Zpu/Zpd Increasing Zpu/Zpd

Vinv

VDD

Vo

Point where Vo = Vin is called Vinv Transfer Characteristics and Vinv can be shifted by altering ratio of pull-up to Pull down impedances

Cascading NMOS Inverters


When cascading logic devices care must be taken to preserve integrity of logic levels i.e. design circuit so that Vin = Vout = Vinv

Determine pull up to pull-down ratio for driven inverter

Assume equal margins around inverter; Vinv = 0.5 Vdd Assume both transistors in saturation, therefore: Ids = K (W/L) (Vgs Vt)2/2 Depletion mode transistor has gate connected to source, i.e. Vgs = 0 Ids = K (Wpu/Lpu) (-Vtd)2/2 Enhancement mode device Vgs = Vinv, therefore
Ids = K (Wpd/Lpd) (Vinv Vt)2/2

Assume currents are equal through both channels (no current drawn by load)
(Wpd/Lpd) (Vinv Vt)2 = (Wpu/Lpu) (-Vtd)2 Convention Z = L/W Vinv = Vt Vtd / (Zpu/Zpd)1/2 Substitute in typical values Vt = 0.2 Vdd ; Vtd = -0.6 Vdd ; Vinv = 0.5 Vdd

This gives Zpu / Zpd = 4:1 for an nmos inverter directly driven by another inv

Pull-Up to Pull-Down Ratio for an nMOS inverter driven through 1 or more pass transistors

Inverter 1 A Vin1 B

Vdd

Vdd C

Inverter 2

Vout2

It is often the case that two inverters are connected via a series of switches (Pass Trans We are concerned that connection of transistors in series will degrade the logic levels in Inverter 2. The driven inverter can be designed to deal with this. (Zpu/Zpd >= 8/1)

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