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PROGRAM: Write The VHDL To Implement A AND GATE.: VHDL Design Lab Sddiet Barwala 1

This document contains VHDL code implementations for basic logic gates and multiplexers/demultiplexers. It includes code for an AND gate, OR gate, NAND gate, NOR gate, half adder, full adder, 1:4 demultiplexer, half subtractor, and 4:1 multiplexer. For each implementation there is a brief description of the VHDL program and circuit diagram of the output.

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Shiv Ahuja
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Download as DOC, PDF, TXT or read online on Scribd
37 views

PROGRAM: Write The VHDL To Implement A AND GATE.: VHDL Design Lab Sddiet Barwala 1

This document contains VHDL code implementations for basic logic gates and multiplexers/demultiplexers. It includes code for an AND gate, OR gate, NAND gate, NOR gate, half adder, full adder, 1:4 demultiplexer, half subtractor, and 4:1 multiplexer. For each implementation there is a brief description of the VHDL program and circuit diagram of the output.

Uploaded by

Shiv Ahuja
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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VHDL DESIGN LAB

SDDIET Barwala

PROGRAM : Write the VHDL to implement a AND GATE.


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity andgate1 is Port ( a : in std_logic; b : in std_logic; c : out std_logic); end andgate1; architecture and1 of andgate1 is begin c<=a and b; end and1;

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

OUTPUT :

CIRCUIT DIAGRAM OUTPUT :

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

PROGRAM : Write the VHDL to implement a OR gate.


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is Port ( a : in std_logic; b : in std_logic; x : out std_logic); end orgate; architecture Behavioral of orgate is begin x<=( a or b); end Behavioral;

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

OUTPUT :

CIRCUIT DIAGRAM OUTPUT :

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

PROGRAM : Write the VHDL to implement a NAND GATE.


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nand1 is Port ( a : in std_logic; b : in std_logic; c : out std_logic); end nand1; architecture universalgate of nand1 is begin c<= a nand b; end universalgate;

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

OUTPUT :

CIRCUIT DIAGRAM OUTPUT :

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

PROGRAM : Write the VHDL to implement a NOR GATE.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity NOR1 is Port ( a : in std_logic; b : in std_logic; x : out std_logic); end NOR1; architecture universalgate of NOR1 is begin x<=a nor b; end universalgate;

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

OUTPUT :

CIRCUIT DIAGRAM OUTPUT :

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

PROGRAM : Write the VHDL to implement a HALF-ADDER.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfadder is Port ( a : in std_logic; b : in std_logic; c : out std_logic; y : out std_logic); end halfadder; architecture half of halfadder is begin c<=a xor b; y<=(a and b); end half;

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

10

OUTPUT :

CIRCUIT DIAGRAM OUTPUT :

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

11

PROGRAM : Write the VHDL to implement a FULL-ADDER.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladder1 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; s : out std_logic; c0 : out std_logic); end fulladder1; architecture Behavioral of fulladder1 is begin s<=(a xor b xor c); c0<=(a and b) or (a and c) or (b and c); end Behavioral;

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

12

OUTPUT :

CIRCUIT DIAGRAM OUTPUT :

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

13

PROGRAM : Write the VHDL to implement a DEMUX 1:4.


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DEMUX is Port ( z : in std_logic; s0 : in std_logic; s1 : in std_logic; a : out std_logic; b : out std_logic; c : out std_logic; d : out std_logic);
B.Tech 6th semester(ECE) 2208092 Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

14

end DEMUX; architecture DM of DEMUX isbegin process(z,s0,s1) begin if s0='0' and s1='0' then a<=z; elsif s0='1' and s1='0' then b<=z; elsif s0='0' and s1='1' then c<=z; else d<=z; end if; end process; end DM;

OUTPUT :

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

15

CIRCUIT DIAGRAM OUTPUT :

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

16

PROGRAM : Write the VHDL to implement a HALF


SUBTRACTOR.
library IEEE;
B.Tech 6th semester(ECE) 2208092 Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

17

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity subtractor is Port ( a : in std_logic; b : in std_logic; c : out std_logic; d : out std_logic); end subtractor; architecture Behavioral of subtractor is begin c<= a xor b; d<=(not a) and b; end Behavioral;

OUTPUT :
B.Tech 6th semester(ECE) 2208092 Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

18

CIRCUIT DIAGRAM OUTPUT :

PROGRAM : Write the VHDL to implement a 4:1 MUX.


B.Tech 6th semester(ECE) 2208092 Rajesh Verma

VHDL DESIGN LAB library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; s0 : in std_logic; s1 : in std_logic; y : out std_logic); end mux; architecture mux1 of mux is begin process(a,b,c,d,s0,s1) variable sel:integer; begin if s0='0' and s1='0' then sel:=1; elsif s0='0' and s1='1' then sel:=1; elsif s0='1' and s1='0' then sel:=2; elsif s0='1' and s1='1' then sel:=3; B.Tech 6th semester(ECE) 2208092

SDDIET Barwala

19

Rajesh Verma

VHDL DESIGN LAB end if; case sel is when 0=> y<=a; when 1=> y<=b; when 2=> y<=c; when others => y<=d; end case; end process; end mux1;

SDDIET Barwala

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OUTPUT :

CIRCUIT DIAGRAM OUTPUT :

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

VHDL DESIGN LAB

SDDIET Barwala

21

B.Tech 6th semester(ECE) 2208092

Rajesh Verma

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