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ADV7xx Limit MCLK Output Frequency

This document provides a matrix of I2C writes that can be used to limit the maximum and minimum MCLK output frequencies from an HDMI receiver. The matrix lists sample rates and their corresponding maximum and minimum MCLK settings in hexadecimal. Columns E, F and G indicate the I2C writes needed for each frequency limit.

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PrashantNirmal
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47 views4 pages

ADV7xx Limit MCLK Output Frequency

This document provides a matrix of I2C writes that can be used to limit the maximum and minimum MCLK output frequencies from an HDMI receiver. The matrix lists sample rates and their corresponding maximum and minimum MCLK settings in hexadecimal. Columns E, F and G indicate the I2C writes needed for each frequency limit.

Uploaded by

PrashantNirmal
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as XLSX, PDF, TXT or read online on Scribd
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The purpose of this document is to supply a matrix of I2C writes which can limit the maximum and minimum

MCL
Columns E, F and G hold the I2C writes for the respective frequency limit.
Matrix of Settings to limit the Maximum MCLK Audio Output Frequency.

Fs (Hz)

MCLK = 128 Fs

32000
32000
44100
44100
48000
48000
88200
88200
96000
96000
176400
176400
192000
192000
192000
Fs (Hz)

4096000
4096000
5644800
5644800
6144000
6144000
11289600
11289600
12288000
12288000
22579200
22579200
24576000
24576000
24576000
MCLK = 256 Fs

32000
32000
44100
44100
48000
48000
88200
88200
96000
96000
176400
176400
192000
192000
192000

Fs (Hz)

5096000
6096000
6644800
7644800
7144000
8144000
12289600
13289600
13288000
14288000
23579200
25579200
25576000
27576000
29576000
Maximum O/P Clock

DPLL MAP,
0xD5 (h)

22
C4
09
6C
3E
94
65
84
82
9E
29
3A
3A
DB
57
DPLL MAP,
0xD5 (h)
DB
11

8192000
9192000 D
8192000
10192000 E
65
11289600
12289600 E
84
11289600
13289600 E
E
82
12288000
13288000
9E
12288000
14288000 E
F
29
22579200
23579200
3A
22579200
25579200 F
F
3A
24576000
25576000
48
24576000
27576000 F
F
94
45158400
47158400
F
9B
45158400
50158400
9D
49152000
51152000 F
9E
49152000
52152000 F
F
A2
49152000
54152000
Matrix of Settings to limit the Minimum MCLK Audio Output Frequency.

MCLK = 128 Fs

32000
44100
48000
88200
96000

Maximum O/P Clock

DPLL MAP,
0xD4[3:0] (h)
C
C
D
D
D
D
E
E
E
E
F
F
F
8
9
DPLL MAP,
0xD4[3:0] (h)

4096000
5644800
6144000
11289600
12288000

Minimum O/P Clock

2096000
3644800
4144000
9289600
10288000

DPLL MAP,
0xD3 (h)
69
A9
CC
DE
E1

DPLL MAP,
0xD4[7:4]
(h)
A

8
A

0
5

176400
192000

Fs (Hz)

22579200
24576000

MCLK = 256 Fs

32000
44100
48000
88200
96000
176400
192000
192000

8192000
11289600
12288000
22579200
24576000
45158400
49152000
49152000

20579200 F0
22576000 F1

Minimum O/P Clock

5192000
8289600
9288000
19579200
21576000
41158400
45152000
43152000

DPLL MAP,
0xD4[3:0] (h)
C3
D9
DE
EF
F1
F8
F8
F8

A
F
DPLL MAP,
0xD5 (h)
4
F

0
D

5
4
F
A

maximum and minimum MCLK output frequencies from the HDMI Receiver.

quency.
DPLL MAP,
0xCF [bit 0 ]

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DPLL MAP,
0xCF [bit 0 ]

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

quency.
DPLL MAP,
0xCF [bit 0 ]

0
0
0
0
0

0
0
DPLL MAP,
0xCF [bit 0 ]

0
0
0
0
0
0
0
0

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