VLSI/FPGA Design and Test CAD Tool Flow in Mentor Graphics
Victor P. Nelson
or. Nightmare on CAD Tool Street
Mentor Graphics CAD Tool Suites
IC/SoC design flow DFT design flow FPGA design flow PCB design flow HDL digital modeling & simulation Analog/mixed-signal modeling & simulation ASIC/FPGA synthesis Vendor-provided (Xilinx,Altera,etc.) back end tools
(select eda Electronic Design Automation)
Auburn user-setup Options
ICFlow2004.3 (2001, 2005.1)
ICFlow tools (Design Architect-IC, IC Station, Calibre) Simulation tools (Modelsim, ADVance MS, Eldo) Synthesis (Leonardo) DFT tools (DFT Advisor, Flextest, Fastscan) Limited access to Quicksim II (some technologies)
EN2002u3 (EN2001)
Design Architect, Quicksim II,Quicksim Pro (Front End) ModelSim & Leonardo (Simulation/Synthesis) Xilinx/Altera tools (Back End)
FPGA (FPGA Advantage, Modelsim, Leonardo)
FPGA Design Flow
Behavioral Design Mentor Graphics Front-End Tools (Technology-Independent) Synthesis Gate-Level Schematic EDIF Netlist Xilinx/Altera/Other Back-End Tools (Technology-Specific) Map, Place & Route Verify Timing Verify Function Verify Function
FPGA Configuration File
IC/ASIC Design Flow
Behavioral Design Verify Function
DFT/BIST & ATPG
Gate-Level Netlist
Verify Function
Transistor-Level Netlist
Verify Function & Timing
DRC & LVS Verification
Physical Layout
Verify Timing
Mask Data
Technology files (all) & standard cell libraries (exc. tsmc018)
ami12, ami05 (AMI 1.2um, 0.5um) tsmc035, tsmc025, tsmc018 (TSMC 0.35um, 0.25um, 0.18um)
Mentor Graphics ASIC Design Kit 3.0
Support for IC Flow & DFT tools:
Synthesis (LeonardoSpectrum) Schematic capture (Design Architect-IC) Design for test & ATPG (DFT Advisor, Flextest/Fastscan) Simulation Modelsim/ADVance MS: VHDL/Verilog/Mixed-Signal models Eldo/Accusim analog (SPICE) models Mach TA post-layout timing Quicksim II, Quicksim Pro (except tsmc025,tsmc018) IC layout & verification (standard cell & custom) IC Station Calibre, SST Velocity
Behavioral Design & Verification
(mostly technology-independent)
Create Behavioral/RTL HDL Model(s) VHDL Verilog SystemC VHDL-AMS Verilog-A
ModelSim
(digital)
Simulate to Verify Functionality
ADVance MS
(analog/mixed signal)
(digital)
Leonardo Spectrum
Synthesize Gate-Level Circuit Technology Libraries Technology-Specific Netlist to Back-End Tools
Digital HDL Simulation
VHDL,Verilog Models Working Library Design_1 Design_2 VITAL IEEE 1164 Resource Libraries
Simulation Setup
ModelSim
Input Stimuli
Result Waveforms
Result Listing
Mixed-Signal HDL Simulation
VHDL,Verilog, VHDL-AMS, Verilog-A, SPICE Models Working Library Design_1 Design_2 VITAL IEEE 1164 Resource Libraries
Simulation Setup
ADVance MS
Input Stimuli
Eldo, Eldo RF Analog (SPICE) Mach TA
EZwave or Xelga View Results
ModelSim Digital (VHDL,Verilog)
ADVance MS Simulation System
ADVance MS kernel supports:
Invoke stand-alone or from Design Architect-IC Mentor Graphics Legacy Simulators (PCB design)
Quicksim II, Quicksim Pro (digital) ASIC: adk_quicksim FPGA/PLD: Xilinx: pld_quicksim, Altera: max2_quicksim Accusim (analog): adk_accusim
VHDL & Verilog: digital (via ModelSim) VHDL-AMS & Verilog-A: analog/mixed signal Eldo/SPICE: analog (via Eldo) Eldo RF/SPICE: analog RF (via Eldo RF) Mach TA/SPICE: high-speed analog/timing
Automated Synthesis
HDL Behavioral/RTL Models Technology Synthesis Libraries FPGA ASIC TechnologySpecific Netlist VHDL, Verilog, SDF, EDIF, XNF Leonardo Spectrum (Level 3) Design Constraints
Level 1 FPGA Level 2 FPGA + Timing
Leonardo ASIC Synthesis Flow
Synthesis Example
Load technology library: tsmc035 (ASIC), or Xilinx Spartan2 (FPGA) Load design file: seqckt.vhd Specify constraints: clock freq, delays, etc. Optimization: effort, performance vs. area Write synthesized netlist output(s):
seqckt_0.vhd : VHDL netlist for ModelSim & DFT seqckt.v : Verilog netlist for import into DA-IC seqckt.sdf : For ModelSim to study timing seqckt.edf : EDIF netlist for 3rd party tools seqckt.xnf : Xilinx netlist for Xilinx ISE
Mentor Graphics DFT Design Flow
Memory & Logic BIST
Boundary Scan
Internal Scan Design
ATPG
ASIC DFT Flow
Synthesized VHDL/Verilog Netlist ATPG Library DFT Advisor VHDL/Verilog Netlist With Scan Elements Fastscan/ Flextest Generate/Verify Test Vectors Insert Internal Scan Circuitry
adk.atpg
Test Pattern File
Physical Design - FPGA
Component-Level Netlist
Xilinx ISE Altera Max Plus 2
Map to FPGA LUTs, FFs, IOBs FPGA/PLD Technology Files
User-Specified Constraints
Place & Route
Generate Programming Data Configuration File
Generate Timing Model Simulation Model
Physical Design ASIC (Std. Cell)
Component-Level Netlist Std. Cell Layouts Floorplan Chip/Block
Mentor Graphics IC Station
Process Data Design Rules
Place & Route Std. Cells
Design Rule Check
Generate Mask Data IC Mask Data
Backannotate Schematic
Layout vs. Schematic Check
Mach TA/Eldo Simulation Model
Design Architect-IC Design Flow
Preparation for Layout
Convert Verilog netlist to Mentor Graphics EDDM netlist format
Invoke Design Architect-IC (adk_daic) Import Verilog feature to create schematic
mapping file $ADK/technology/adk_map.vmp
Open the generated schematic Prepare design viewpoints for layout
May also create schematic diagrams for handdesigned circuits gate and/or transistor level
Components from ADK library
