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8x1 Mux Using 2x1mux PDF

This document provides VHDL code to implement multiplexers using different modeling techniques. It includes: 1) A 2x1 multiplexer using data flow and behavioral modeling. 2) A 4x1 multiplexer using behavioral and structural modeling, with the 2x1 multiplexer as a component. 3) An 8x1 multiplexer using structural modeling with 4x1 and 2x1 multiplexers as components.

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Prabh Preet Singh
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4K views3 pages

8x1 Mux Using 2x1mux PDF

This document provides VHDL code to implement multiplexers using different modeling techniques. It includes: 1) A 2x1 multiplexer using data flow and behavioral modeling. 2) A 4x1 multiplexer using behavioral and structural modeling, with the 2x1 multiplexer as a component. 3) An 8x1 multiplexer using structural modeling with 4x1 and 2x1 multiplexers as components.

Uploaded by

Prabh Preet Singh
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ELCT601 Digital System Design Spring 2013 Sheet # 3 Solution

Dr. M. Abdel Ghany Eng. Salma Hesham

1. Implement a 2x1 multiplexer once using VHDL data flow modeling and once using behavioral modeling. Test your multiplexer through a VHDL test bench simulation.

Data Flow Modeling:


entity Mux2x1 is port( A,B,S: in std_logic; F: out std_logic); end Mux2x1; architecture Dataflow of Mux2x1 is begin F <= ((not S) and A) or (S and B); end Dataflow;

Behavioral Modeling:
entity Mux2x1 is port( A,B,S: in std_logic; F: out std_logic); end Mux2x1; architecture Behavioral of Mux2x1 is begin Process(A,B,S) Begin if(S='0')then F<=A; else F<=B; end if; end Process; end Behavioral;

2. Implement a 4x1 multiplexer once using VHDL structural modeling and once using behavioral modeling. Use the 2x1 multiplexer implemented in part (1) for the structural modeling. Write a VHD test bench to test your 4x1 multiplexer.

Behavioral Modeling:
entity Mux4x1 is port( A,B,C,D: in std_logic; S: in std_logic_vector(1 downto 0); F: out std_logic); end Mux4x1; architecture Behavioral of Mux4x1 is begin Process(A,B,C,D,S) Begin if(S="00")then F<=A; Structural Modeling: elsif(S="01")then F<=B; elsif(S="10")then F<=C; entity Mux4x1 is else F<=D; port( A,B,C,D: in std_logic; end if; S: in std_logic_vector(1 downto 0); end Process; F: out std_logic); end Behavioral; end Mux4x1; architecture Structural of Mux4x1 is component Mux2x1 is port( A,B,S: in std_logic; F: out std_logic); end component; Signal F1, F2: std_logic; Begin M1: M2: M3: end Mux2x1 port map(A,B,S(0),F1); Mux2x1 port map(C,D,S(0),F2); Mux2x1 port map(F1,F2,S(1),F); Structural;

3. Implement an 8x1 multiplexer using VHDL structural modeling. Use the 4x1 multiplexer together with the 2x1 multiplexer implemented in part (1) and (2) as shown in the figure below. Write a VHD test bench to test your 4x1 multiplexer.

Structural Modeling:
entity Mux8x1 is port( A: in std_logic_vector(7 downto 0); S: in std_logic_vector(2 downto 0); F: out std_logic); end Mux8x1; architecture Structural of Mux8x1 is component Mux2x1 is port( A,B,S: in std_logic; F: out std_logic); end component; component Mux4x1 is port( A,B,C,D: in std_logic; S: in std_logic_vector(1 downto 0); F: out std_logic); end component; Signal F1, F2: std_logic; Begin M2: Mux4x1 port map(A(0),A(1),A(2),A(3),S(1 downto 0),F1); M3: Mux4x1 port map(A(4),A(5),A(6),A(7),S(1 downto 0),F2); M1: Mux2x1 port map(F1,F2,S(2),F); end Structural;

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